Transmitter circuit comprising timing deskewing means

Details Transmitter circuit comprising timing deskewing means Transmitter circuit comprising timing deskewing means

2001-11-06

2002-11-12

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S086000, C326S090000

Reexamination Certificate

active

06480021

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the transmission of digital data. More particularly, the invention relates to a high-speed data transmission between integral circuits (ICs) or chips.
2. Description of Related Art
Over last years, operating speed of computer processors has increased dramatically, resulting in additional demands on speeds of transmission of digital data. This has lead to very high frequencies in data transmission lines. At high frequencies some effects occur not observed at low frequencies and connected with the behavior of receiving loads (wires, circuit boards and integrated-circuit packages that make up a digital product).
Small lengths of signal conductors such as shown in
FIG. 3
a
, can act like analog transmission lines, producing reflections which may distort received signals as shown in
FIGS. 4
a
-
4
c
and produce effects such as ringing, bouncing, and overshoot. Such distortion, combined with other sources of noise, such as cross-talk between conductors as shown in
FIG. 5
b
, may produce faulty operations in circuits which otherwise appear to have satisfactory design specifications. That is, at high frequencies load elements directly affect electrical performance. Accordingly, such transmission line effects, especially with respect to circuits having critical timing requirements for signal reception, are becoming the matter of increasing importance.
One high frequency effect of particular concern in the present invention is illustrated in
FIG. 5
a
. When a period of alteration of a signal, i.e. data rate, approaches the settling time of a signal on the data line, inter-symbol interference (ISI) occurs depending on the history of previously transmitted bits. Inter-symbol interference refers to the timing and signal quality impact of the previous state of the data line on the current state.
Charge storage both in the transmitting devices and the state of the transmission line causes a delay in the signal and a change in the slew rate. For example, if a transmitter is driving a very high frequency signal that is 1, 0, 1, 0 then each cycle the driver and transmission line must change state—with very high frequency systems each of these signals will approximate a triangular wave. When the same system transmits 1, 1, 1, 0 then the level of the signal which is already a 1, will be higher than in the case where the state is inverting on every cycle.
Thus, as seen in
FIG. 5
a
, a signal will reach different values depending on how long the present state of the signal is maintained, whereby the cross-point of the signal and the reference shifts, thus causing a skew. To eliminate the skew, a history of the signal shall be analysed and a clock adjusted accordingly.
Another high frequency effect of particular concern in the present invention as shown in
FIGS. 4
a
-
4
c
, is that of reflections which also cause ISI in the line. ISI is a function of the mismatch between the driver impedance, the transmission line impedance, and the transmission line length.
Moreover, a transmission line is generally not uniform. It can include unequal-impedance parts (as shown schematically by
32
and
33
) such as conductive traces on different boards or in different layers of the same board, connectors, and/or cables. Interfaces between these parts will also produce reflections which will contribute in affecting the signal.
FIG. 3
a
illustrates a conventional communication link configuration with a driver
31
and a receiver
34
coupled to a transmission line comprising portions
32
and
33
of different impedance Z
1
and Z
2
. Data that applied to an input terminal of the driver
31
appears at an output terminal of the driver
31
, allowing a data signal, such as shown in
FIG. 4
a
, to be transferred via the transmission line
32
. If there is a significant impedance mismatch between the transmission lines
32
and
33
, a reflection from the line discontinuity (on the border of portions
32
and
33
) can occur, so that the signal actually transmitted will be as
FIG. 4
b
, not as shown in
FIG. 4
a
(where t
1
is a propagation time in the line portion having impedance Z
1
). The presence of reflections in a transmission line can cause an increase in the skew and a corresponding decrease in the overall bus transfer rate. Thus, it would be beneficial to have a device adapted to handle these kind of reflections, to enhance thereby bus transfer rate.
This effect can occur also when the impedance of a transmission line does not match the impedance of a terminating load
35
on the driving or receiving end of the line. Ideally, a terminating load R
2
will sink a transmitted signal immediately upon the signal arriving at the load. However, the terminating load often does not match the transmission line impedance because of variations in output resistance which can result from the production variations of elements and/or variations in power supply voltage and/or temperature. In this case the load will sink only a portion of the signal upon the signal's initial arrival. The remaining portion of the signal will be reflected back onto the transmission line after a time t
1
+t
2
, so that the signal at the load
35
would be as shown in
FIG. 4
c
(left part). If the receiving circuit provides a terminating load R
2
that matches the impedance Z
2
of the transmission line, the reflected signal portion will sink on reaching the receiving end
34
. Otherwise, the reflected signal portion will be partially reflected again and thus return to the receiving end after a time
3
t
1
+t
2
as shown in
FIG. 4
c
(right part). Thus, substantial portions of the reflected signal can go back and forth until they damp in the transmission line. Each time the reflected signal portion comes to the receiving end it affects the main signal by producing an additional skew. This will reduce the precision with which the signal can be measured and therefore will not allow increasing the speed of data transmission.
Efforts were made to eliminate, or at least greatly reduce, signal reflections by matching, insofar as possible, the impedance of a terminating load
35
and that of a transmission line portions
32
and
33
.
Known are various means for impedance matching disclosed in U.S. Pat. Nos. 4,719,369; 5,134,311; 5,162,672; 5,811,197; 5,602,494; 6,191,663; 6,175,250; 6,157,215; 6,130,563; 6,127,862; 6,118,310; 6,087,853; 6,060,907; 5,955,894.
Generally, these patents disclose IC output drivers comprising a circuit which compensates for the variations in output resistance.
With the driver according to U.S. Pat. No. 6,118,310, a portion of the signal reflected on the receiving end back onto the transmission line will sink on its driving end and thus not affect the received signal. However, this driver will not help in sinking the above-mentioned reflections produced at the interfaces between the unequal-impedance parts of the transmission line. These reflections can go back and forth between the receiver and respective interface, not reaching the driver end where they could be terminated.
Thus, even though impedance-matching means are used in the prior art, reflections and inter-symbol interference still exist and affect the signal by producing additional skew. Furthermore, topological restrictions and transmission line discontinuities can make impedance balancing impractical or very difficult (and therefore costly) to implement. Even more significantly, signal distortions associated with transmission line effects are due to both reflections and re-reflections of signals, and taking steps to suppress or reduce both type of reflections may be even more difficult, costly and less useful.
Known is a skew reducer described in U.S. Pat. No. 5,953,521, wherein, to compensate for the skew caused by an inter-symbol interference in a signal pattern transmitted, predetermined delays are applied to a data to be transmitted via a transmission line. However, this means can use only two predetermined delay values, while in practice

Affiliated with

Also associated with

Rating

Transmitter circuit comprising timing deskewing means does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Transmitter circuit comprising timing deskewing means, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Transmitter circuit comprising timing deskewing means will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2968882