Transmitter architecture for high-speed communications

Details Transmitter architecture for high-speed communications Transmitter architecture for high-speed communications

2005-11-30

2009-08-04

Tran, Khanh C (Department: 2611)

Pulse or digital communications

Transmitters

C708S323000

Reexamination Certificate

active

07570704

ABSTRACT:
A transmitter architecture includes an equalizer and a D/A converter, for high-speed transmission of data across a channel. The equalizer includes a two-tap MAC as part of an N-stage, two-way interleaved FIR filter. The two-tap MAC provides substantial power and area savings over conventional MAC-based FIR filter designs, and may be implemented in short or long communications channels. The D/A converter is decoupled from the equalizer. Its N-bit, binary-weighted driver includes matched unit current generation cells, all of which are fully utilized during each digital-to-analog conversion. The D/A converter remains unchanged, even when the characteristics of the equalizer are changed.

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