Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
1998-10-30
2002-10-08
Ray, Gopal C. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S315000, C710S052000, C709S250000, C370S464000
Reexamination Certificate
active
06463498
ABSTRACT:
TECHNICAL FIELD
The present invention relates to the improvement of communications network port performance and, in particular, to a method and system that decreases I/O latency and increases data throughput in communications network-based client/server mass storage solutions.
BACKGROUND OF THE INVENTION
The Fibre Channel (“FC”) is an architecture and protocol for a data communication network for interconnecting a number of different combinations of computers and peripheral devices. The FC supports a variety of upper-level protocols, including the small computer systems interface (“SCSI”) protocol. A computer or peripheral device is linked to the network through an FC Port and copper wires or optical fibres. An FC Port includes a transceiver and an interface controller, and the computer peripheral device in which the FC Port is contained is called a “host.” The FC Port exchanges data with the host via a local data bus, such as a peripheral computer interface (“PCI”) bus. The interface controller conducts lower-level protocol exchanges between the Fibre Channel and the computer or peripheral device in which the FC Port resides.
The FC is becoming increasingly important as a means to interconnect computers and peripheral storage devices. In such applications, an FC arbitrated loop topology is commonly employed. In an FC arbitrated loop, an FC node contends for control of the FC arbitrated loop and, upon gaining control, opens a channel to another FC node and exchanges data with that FC node in half-duplex or full-duplex mode. Peripheral mass storage devices commonly receive and respond to write and read commands from a host computer according to the SCSI protocol. Thus, in the common FC arbitrated loop topology for interconnecting host computers with peripheral mass storage devices, the host computer and peripheral mass storage devices exchange read and write commands and data through the SCSI protocol implemented on top of the Fibre Channel protocol.
A read operation may be initiated by a host computer, called an “initiator,”and executed by a peripheral mass storage device, called a “target,” which then returns the data requested in the read command back to the initiator. When the initiator and target communicate via the SCSI protocol mapped onto the FC protocol over an FC arbitrated loop topology, the issuance and execution of the read command involves three main phases. In the first phase, the initiator contends, or arbitrates, for control of the FC arbitrated loop and then sends the read command to the target. In the second phase, the target responds by arbitrating for FC arbitrated loop control and then sending the requested data back to the initiator. In the third phase, the target either maintains control of the FC arbitrated loop while preparing a final response sequence and then sends the response sequence back to the initiator, or the target surrenders control of the arbitrated loop, prepares a response sequence, again arbitrates for control of the FC arbitrated loop, and finally sends the response sequence back to the initiator. In the first alternative, the target blocks all other use of the FC arbitrated loop while it prepares the response sequence, and consequently, the throughput of the FC arbitrated loop is as a whole is degraded. In the second alternative, the target must arbitrate twice for FC arbitrated loop control in order to complete the read command, and thus the time for completion of the read command, or latency of the read command, is increased. FC port designers and manufacturers have therefore recognized the need to more intelligently execute SCSI read operations within the context of the FC arbitrated loop topology in order to avoid unnecessary degradation of FC arbitrated loop throughput and unnecessary increase in I/O command execution latency.
SUMMARY OF THE INVENTION
The present invention provides a Fibre Channel (“FC”) interface controller for use in FC Ports interconnected by an FC arbitrated loop, that implements, in hardware, an efficient method for executing read commands in order to avoid unnecessary Fibre Channel throughput degradation and unnecessary increase in I/O latencies. In the improved method, the FC host containing an FC Port implemented with the improved interface controller of the present invention prepares a description of the data requested by a received read operation command into host memory buffers and assembles an FCP_Response sequence at the same time. The FC host then provides the improved interface controller with a data structure that includes references to the host memory buffers that contain the data requested by the read operation command and that also includes a reference to the description of the FCP_Response sequence. The FC Port implemented using the improved interface controller, upon receiving the data structure from the host, arbitrates for control of the FC arbitrated loop, returns the data requested by the read operation command to the initiator of the read operation command in an FC data sequence, and then immediately transmits to the initiator the already prepared FCP_Response sequence. By this method, the FC Port including the improved interface controller avoids arbitrating twice for control of the FC arbitrated loop in order to respond to the received read operation command and also avoids the increased I/O latency incurred by certain currently-available interface controllers when they return control to the host for preparation of the FCP_Response sequence. The improved interface controller transfers both the FCP data sequence and the FCP_Response sequence directly from host memory buffers to the Fibre Channel arbitrated loop, rather than unnecessarily storing and forwarding the FCP data sequence and FCP_Response sequence.
REFERENCES:
patent: 5727218 (1998-03-01), Hotchkin
patent: 5809328 (1998-09-01), Nogales et al.
patent: 6209023 (2001-03-01), Dimitroff et al.
patent: 6314477 (2001-11-01), Cowger et al.
Cowger Bryan J
Wakeley Matthew P
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