Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1998-01-20
2000-11-07
Hua, Ly V.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
714 48, 714 56, 714 57, G06F 1120, G01R 3138
Patent
active
061451029
ABSTRACT:
A computer may have a management bus installed, where the management bus is coupled to sensors which monitor status of components of the computer. The management bus may also be coupled to a management bus processor, where the management bus processor receives status information from the management bus concerning status of components of the computer. An interface between the management bus and the network subsystem permits transmission of an error message in the event that the computer has a failure which inactivates the system CPU, the system bus, the system memory, or the system power supply.
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Ben-Michael Simoni
Klein Philippe
Menachem Avraham
Shvimmer Sarit
Compaq Computer Corporation
Hua Ly V.
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