Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-08-26
2001-04-17
Beausoleil, Robert (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S120000, C709S232000
Reexamination Certificate
active
06219733
ABSTRACT:
TECHNICAL FIELD
The present invention relates i n general to data processing systems, and in particular, to transmission lines within integrated circuit technologies.
BACKGROUND INFORMATION
The construction of a computer system has evolved to a modular architecture, where various subsystems are implemented on daughterboards, which are connected to the motherboard. The motherboard is the main circuit board containing the primary components of the computer system. This board often contains the processor, main memory, support circuitry, and a bus controller and connector. Daughterboards, including expansion memory, input/output, and multiprocessor boards, may attach to the motherboard via a plurality of bus connectors.
Considerable effort has been made to speed up the various integrated circuits, which make up a computer system. However, as integrated circuit technologies shrink and their performance increases, the printed circuit board becomes the gating and most significant single factor limiting the speeds by which signals are transmitted on the bus lines connecting the various integrated circuits. The cycle budget for a synchronous bus can be broken into three contributing factors. One, is driving and receiving integrated circuit delays with respect to the system clock. Another is the system clock skew. The third contributor is the card net delay, which is the time required to propagate signals over the transmission lines within the network of bus lines connecting the various integrated circuits. However, improvements in the card net delay have been few.
The net delay is principally dictated by the printed circuit board (“PCB”) technology, the topology of the net, and the rise and fall times of the driver circuitry. The fastest possible net is a point-to-point net. The delay of such a point-to-point net is the propagation speed of the board times the net link, plus the delay lost to a slowing of the rise and fall times due to the capacitive load introduced by the receiver. Additionally, a point-to-point solution results in the need for added buffering and additional control logic, which results in a more expensive solution. Furthermore, additional cycles are needed to implement such point-to-point nets.
Multidrop nets are more common in higher volume, lower cost systems, and are prevalent on data buses. Such nets have loads that are bidirectional. The main challenge on multidrop nets is to lay them out and route them such that the signal reflections do not significantly distort waveforms in the critical threshold regions of the receiving devices. A second challenge is arriving at a topology that optimizes all the scenarios such that delays due to reflections are minimized.
Once the integrated circuit technologies, clock distribution and mechanical requirements have been established, the card designer is left with limited possibilities in routing the net so as to not only assure that they run reliably but also optimized for speed. The normal cost of reliability of the net is additional delay.
SUMMARY OF THE INVENTION
The present invention addresses the foregoing problems by optimizing a reflection profile of a data net. A reflection profile is the addition of reflections added to the originally received waveform that produces the observed waveform shape at the receiver. The optimization of the waveform profile is the reduction or movement of reflections in order to clean up threshold regions and speed up the worst case net delay scenario. Such a scenario is the waveform profile at each receiver when one of the drivers owns the bus.
In an embodiment of the present invention, a bus cable is connected between two daughter cards (daughterboards) mounted on a system board (motherboard) so as to provide a complete loop when the integrated circuits on the daughter cards are also connected to an integrated circuit on the motherboard. An advantage of the present invention is that no modifications need to be made to the motherboard. Instead, the daughter cards are replaced with upgraded daughter cards having the connections from the integrated circuits to the connectors, which are then connected with the bus cable. This can be accomplished with a cable connected at the top of the daughter cards, thus eliminating any need to modify or replace the motherboard, which can be considerably more troublesome and expensive.
One advantage with this implementation is that the motherboard need not be replaced when the user upgrades to a system whereby multiple daughter cards are now needed. Instead, merely the daughter cards are replaced with the daughter cards modified in accordance with the present invention, which are then connected using the bus cable.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.
REFERENCES:
patent: 3751591 (1973-08-01), Radcliffe et al.
patent: 4467436 (1984-08-01), Chance et al.
patent: 5146587 (1992-09-01), Francisco
patent: 5182798 (1993-01-01), Francisco
patent: 5185866 (1993-02-01), Francisco
patent: 5438297 (1995-08-01), Rahal-Arabi et al.
patent: 5450603 (1995-09-01), Davies
Appel William Dale
Co Gricell
Liu Franklin Mark
Beausoleil Robert
International Business Machines - Corporation
Kordzik Kelly K.
Leeuwen Leslie A. Van
Vo Tim
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