Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
1998-03-17
2001-05-01
Young, Brian (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S083000, C326S087000
Reexamination Certificate
active
06225819
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuits, and, more particularly, to improving the output of such circuits during state transitions.
2. Discussion of the Related Art
An output buffer of an integrated circuit is generally provided for transferring signals from an internal logic circuit, to an output of the integrated circuit. The term “buffer” may also refer to an entire integrated circuit dedicated solely to driving signal lines, which would include one or more output buffers. The output of the integrated circuit may be connected to a near-end of various wires, cables or printed circuit board traces of a single circuit board, or between multiple printed circuit boards through a backplane. The foregoing structures connected to the output buffer may be generally described as an electrical transmission line, especially when the output buffer is driving electrical signals with fast edge rates. In addition, the far-end of the transmission line may be connected to an input terminal of another integrated circuit. In the context of the communication of digital signals, the varying electrical characteristics of the transmission line, as well as the far-end circuit input, gives rise to a number of problems.
One problem pertains to transmission line effects. If the far-end is improperly terminated and/or open circuit, an impedance mismatch and consequent signal reflections may occur. In the open circuit context, transitions of the output signal generated by the output buffer may result in undershoots and overshoots relative to the desired steady state value. These signal variations may exceed the maximum rated input voltage of any receiving unit to which the transmission line is connected. In addition, the overshoots and undershoots may cross the threshold voltage of the receiver several times. This threshold crossing may result in the generation of system errors (e.g., logic errors).
To better appreciate other problems, further background is provided. The transmission line has a characteristic impedance Z
o
. In addition, a real world output buffer exhibits an output impedance, which will be designated generally in this patent application as R
s
. In practical implementations, the output buffer exhibits a different impedance profile depending on whether its output is transitioning high-to-low or low-to-high. Specifically, the buffer has a first output impedance profile when the output signal undergoes a low-to-high transition, contributed largely by the characteristics of the pullup transistor. In addition, the buffer has a second output impedance profile when the output signal undergoes a high-to-low transition, contributed largely by the pulldown transistor.
The degree to which the output buffer impedance matches the transmission line impedance bears on at least two characteristics of the buffer output signal: (i) a so-called “plateau” voltage level, and (ii) the amount of undershoot and overshoot (i.e., ringing). The plateau level refers to an intermediate step exhibited in the output signal of the buffer while transitioning, for example, from a high logic state to a low logic state (or vice versa). That is, for example, a high-to-low transition does not necessarily occur sharply but rather commences at a high level voltage, falls to and maintains at an intermediate voltage for a time, and then falls to a low (end state-steady state) voltage level. This intermediate step or plateau is caused by the fact that the output impedance of the buffer R
s
is effectively in series with the characteristic impedance of the transmission line Z
o
, which forms a voltage divider. The height of the step or plateau depends on the relative values of R
s
and Z
o
, and the length or duration of the step depends upon the round trip electrical delay of the output signal along the transmission line.
One problem arising in view of the foregoing is that the voltage level of the plateau may fail to define either a logic high or a logic low (i.e., may be an undefined voltage level). An output signal at this voltage level may generate spurious results at the input of any circuit to which it is connected, typically at the near end of the transmission line, causing system errors as well as causing excessive power dissipation. In addition, the problems associated with ringing in the output signal are well known (i.e., overvoltage, threshold crossing, etc., as described above).
One approach to these problems is described in U.S. Pat. No. 5,559,447 entitled “Output Buffer with Variable Output Impedance” issued Sep. 24, 1996, and commonly owned by the assignee of the present invention. In U.S. Pat. No. 5,559,447, an output buffer is disclosed that is controlled between two fixed output impedance values based on a threshold output signal voltage level. However, as switching speeds continue to increase, there continues to be a need for improved output impedance control.
Accordingly, there is a need to provide an improved output buffer that minimizes or eliminates one or more of the problems set forth above.
SUMMARY OF THE INVENTION
The present invention overcomes the disadvantages of conventional output buffers by providing an output buffer with a variable output impedance to match the transmission line. The buffer configures its output impedance in stages. First, the output buffer is configured to exhibit a relatively low output impedance during a first stage or portion of an output transition. This ensures the required plateau voltage is reached when driving a low impedance T Line. During a second stage or portion of the output transition that occurs after the first portion, the output buffer matches its output impedance to a set fraction of that of the transmission line. In this regard, the buffer is configured to have a reduced plateau level, approximately 1.2 volts or lower in one embodiment, to reduce the time during which the output voltage level is undefined (i.e., the transition time through the undefined voltage levels). During a third stage or portion of the output transition that occurs after the second portion, the output buffer is configured to increase its output impedance, thereby increasing the damping of noise oscillations which may otherwise result from the return wave from the far-end of the transmission line.
An output buffer according to the invention may include an output stage receiving an input signal and generating an output signal on an output node in response thereto. In addition, the output buffer may include means for adjusting an output impedance of the buffer as a function of a transmission line impedance over a predetermined range of output node voltages.
In a preferred embodiment, the adjusting means may include a control circuit and a driver. The control circuit is configured to receive the output node voltage and generate a control signal on a control node. The control signal varies in magnitude according to the magnitude of the output node voltage. The driver, preferably, is in electrical communication with the output node and has a conductivity that varies according to the control signal. Variations of the driver conductivity are operative to adjust the output impedance of the buffer. In a preferred embodiment, this is accomplished by disposing the driver in parallel electrical relation with the output stage, and, more particularly, in parallel with a pullup or pulldown transistor thereof. The control circuit, in a preferred embodiment, may include a voltage follower circuit or an equivalent thereof configured to maintain a nominal voltage offset between the control signal and the output signal.
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patent: 5057715 (1991-10-01
Rees David B.
Withrington Jonathan
Cypress Semiconductor Corp.
Le Don Phu
Maiorana P.C. Christopher P.
Young Brian
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