Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2006-04-25
2006-04-25
Perveen, Rehana (Department: 2112)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S033000, C710S034000, C710S035000
Reexamination Certificate
active
07035956
ABSTRACT:
A communications control circuit includes: a common work RAM storing communications data; an address register; a data-set-count register; an information register; an address counter; a data set counter; a RAM control circuit reading transmission data from a common memory in response to a transmission data request, writing reception data to the common memory in response to a reception data request, and generating a counter clock; a transmission circuit; a reception circuit; and a communications controller setting the address counter to an address upon transmission/reception and a counter to a number of sets of data, and if transmission/reception has been successful, writing the address back to the address register and the number of sets of data back to the register.
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patent: 5983289 (1999-11-01), Ishikawa et al.
patent: 6111592 (2000-08-01), Yagi
patent: 62-60044 (1987-03-01), None
patent: 2-32650 (1990-02-01), None
patent: 2-298140 (1990-12-01), None
Patel Nimesh
Perveen Rehana
Sharp Kabushiki Kaisha
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