Transmission circuit of a line encoded signal on a telephone lin

Details Transmission circuit of a line encoded signal on a telephone lin Transmission circuit of a line encoded signal on a telephone lin

1995-04-18

1998-05-12

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375376, H04L 700, H04L 2536, H04L 2540

Patent

active

057517754

ABSTRACT:
A full duplex transmission circuit for a signal having alternating synchronization words with data words. The circuit comprising a phase-locked loop including a frequency synchronizer adapted to provide an emission clock signal. A sampling signal having its phase locked on the shift between an emitted signal and a received signal is generated using a clock signal provided by the phase-locked loop. The circuit includes circuitry for imparting to the frequency synchronizer a frequency multiplier function to reduce a duration of phase skips of the sampling signal.

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IEEE Journal of Solid-State Circuits, vol. 22, No. 2, Apr. 1, 1987, New York US pp. 255-261, Deog-Kyoon Jeong, et al. "Design of PLL-Based Clock Generation Circuits".
Nachrichtentechnische Berichte, No. 5, Nov. 1, 1988, Bachnang DE pp. 40-49, Volker Hespelt, et al. "Zur Synchronisation des Empfangers fur den ISDN-Basisanschluss".

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