Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Output switching noise reduction
Reexamination Certificate
2007-09-11
2007-09-11
Le, Don (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Output switching noise reduction
C326S083000
Reexamination Certificate
active
11132385
ABSTRACT:
Providing a transmission circuit, which can transfer data normally with high speed even toward a host controller and a device, which does not meet design requirements defined in the standard, a data-transfer control device and electronic equipment. A current source coupled between a first source VDD and a node ND10; a first transistor SW1formed between the node ND10and a DP terminal; a second transistor SW2formed between the node ND10and a DM terminal; a first buffers outputting a first control signal HS_DPout2to the gate of the first transistor SW1; and a second buffer outputting a second control signal HS_DMout2to the gate of the second transistor SW2; are included. When any of the first control signal HS_DPout2and the second control signal HS_Dmout2is set active, other of the control signals is set non-active. Each of the buffers includes a first inverter INV1and a second inverter INV receiving an output from the first inverter INV1. A capacitance-arrangement circuit between the inverters INV1and INV2is installed.
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Le Don
Oliff & Berridg,e PLC
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