Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
1996-12-23
2001-07-24
Lane, Jack A. (Department: 2185)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S202000, C711S203000, C711S206000, C711S207000
Reexamination Certificate
active
06266755
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates in general to computers and in particular, to the management of the computer's memory.
Virtually all computers today utilize what is known as virtual memory to provide more memory than physically available. A virtual address space is a set of memory addresses available for a program to use. Typically, the virtual address space is divided into blocks of equal size called pages. These blocks must be converted or mapped into the computer's physical memory. The mapping is performed using a translation buffer.
The translation buffer compares current virtual page address of a current instruction with previously translated instructions. If a match is found, that entry in the translation buffer is selected and its associated physical page address is provided. To improve throughput, the entries in the translation buffer are compared in parallel.
It is essential that the translation buffer does not contain multiple copies of identical virtual pages addresses. This can cause multiple entries to be selected, which may result in currents shorts that can cause damage to the computer.
To prevent conflicting entries, some systems implement an analog circuit that disables the translation buffer if several entries are simultaneously selected. However, the number of conflicting entries needed to trigger shutdown is imprecise, depending on circuit variations. Further, shutting down and resetting the translation buffer causes delay in the computer.
Thus, there is a need for providing a translation buffer that can detect multiple entries accurately as well as resolving discrepancies without hindering performance.
SUMMARY OF THE INVENTION
The present invention offers a highly efficient mechanism for implementing translations of virtual memory addresses into physical memory.
In one embodiment, the present invention provides translation buffer that can accurately prevent identical virtual page addresses from being stored in the translation buffer without having to shut down and reset the translation buffer.
REFERENCES:
patent: 4473878 (1984-09-01), Zolnowsky et al.
patent: 4812969 (1989-03-01), Takagi et al.
patent: 4953073 (1990-08-01), Moussouris et al.
patent: 5226133 (1993-07-01), Taylor et al.
patent: 5237671 (1993-08-01), Freitas et al.
patent: 5263140 (1993-11-01), Riordan
patent: 5325507 (1994-06-01), Freitas et al.
patent: 5396448 (1995-03-01), Takayanagi et al.
patent: 5420992 (1995-05-01), Killian et al.
patent: 5526504 (1996-06-01), Hsu et al.
patent: 5572704 (1996-11-01), Bratt et al.
patent: 5574877 (1996-11-01), Dixit et al.
patent: 5604909 (1997-02-01), Joshi et al.
patent: 5619672 (1997-04-01), Sutu et al.
patent: 5632025 (1997-05-01), Bratt et al.
patent: 5740402 (1998-04-01), Bratt et al.
patent: 5954815 (1999-09-01), Joshi et al.
patent: 6-202954 (1994-08-01), None
Cocke, et al., “The Evolution Of RISC Technology At IBM,” IBM J. Res. Develop., vol. 34 No. 1, pp. 4-36 (Jan., 1990).
Kane et al., MIPS RISC Architecture, pp. ix to xiv, 4-8 to 4-30, Prentice-Hall, Inc. (1992).
Lane Jack A.
MIPS Technologies Inc.
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