Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1998-01-30
2002-12-10
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S202000, C711S206000, C365S189070
Reexamination Certificate
active
06493790
ABSTRACT:
BRIEF DESCRIPTION OF THE INVENTION
This invention relates generally to translation-lookaside buffers (TLBs). More particularly, this invention relates to a TLB with a reference current circuit that improves the processing yield of the TLB.
BACKGROUND OF THE INVENTION
FIG. 1
illustrates a general purpose computer
20
that includes a central processing unit (CPU)
22
that communicates with primary memory (generally random-access memory or RAM)
24
and secondary memory (generally disk storage)
26
over a system bus
28
. Input/output (I/O) devices
30
, such as monitors or keyboards, are also connected to system bus
28
.
CPU
22
executes one or more computer programs stored in primary memory
24
. Most instructions and data in a computer program have a corresponding virtual address. Each virtual address is then translated to a physical address located in primary memory
24
. If the required information is not in primary memory
24
, then a page fault occurs, and CPU
22
loads the required information from secondary memory
26
into primary memory
24
.
The use of virtual addresses in a computer is a technique commonly referred to as “virtual memory.” Practically all general purpose computers rely upon virtual memory. Virtual memory allows a computer to execute a program that includes a range of addresses that may exceed the primary memory capacity of the computer. Thus, programmers are not restricted by primary memory size considerations, and the programs are portable between hardware environments with different primary memory capacities.
Translation of virtual addresses to physical addresses is performed by an operating system running on general purpose computer
20
using page tables stored in primary memory
24
or secondary memory
26
. The page tables contain a set of page table translation entries, each of which maps a virtual address to a corresponding physical address. Each page table translation entry contains a virtual page number associated with the virtual address and a physical page number associated with the physical address corresponding to the virtual address. The operating system accesses the page tables whenever a virtual-to-physical address translation is required.
To improve the performance of page tables, modem computers include a special cache, called a translation-lookaside buffer (TLB), that keeps track of recently used translations. Referring to
FIG. 1
, computer
20
includes a TLB
32
coupled to CPU
22
.
FIG. 2
illustrates a simplified block diagram of TLB
32
. TLB
32
comprises a content-addressable memory (CAM)
34
and a random-access memory (RAM)
38
. CAM
34
comprises a set of CAM rows
35
each containing a plurality of CAM cells
31
. Each CAM row
35
contains a virtual page number comprising the higher-order bits of a virtual address. RAM
38
comprises a set of RAM rows
39
each containing a plurality of RAM cells
33
. Each RAM row
39
contains a physical page number comprising the higher-order bits of the physical address. Each RAM row
39
is paired with one of the CAM rows
35
. Each RAM row
39
contains the physical page number corresponding to the virtual page number contained in the paired CAM row
35
.
Continuing to refer to
FIG. 2
, TLB
32
performs a translation of a virtual address to a physical address as follows. First, CAM
34
is provided with the virtual page number of the virtual address to be translated. Next, each CAM row
35
in CAM
34
compares the virtual page number provided to the CAM with the virtual page number stored in the row. If the provided virtual page number matches the stored virtual page number (i.e., a CAM row “hit”), CAM row
35
asserts a match signal. If the page numbers do not match (i.e., a CAM row “miss”), the match signal is not asserted. If a CAM row hit occurs, the match signal generated by CAM row
35
causes the corresponding RAM row
39
to output the physical page number stored in the row. The physical page number is then used by CPU
22
to construct the physical address.
In a TLB using pseudo-differential sensing, the match signal is generated by a match sense amplifier (not shown) in CAM row
35
. The match sense amplifier compares the CAM signal generated by the CAM cells in CAM row
35
to a reference signal generated by a reference circuit (not shown) to determine whether a CAM row hit or miss occurred. Specifically, the match sense amplifier determines whether the voltage or current of the CAM signal is greater or less than that of the reference signal. If a CAM row hit is determined to have occurred based on this comparison, the match sense amplifier asserts the match signal. Otherwise, the match sense amplifier does not assert the match signal.
One problem experienced by prior art TLBs using pseudo-differential sensing is a lack of “tracking” between the CAM signal and reference signal. The voltage or current of the CAM and reference signals is subject to change due to variations in the process used to fabricate TLB
32
or in the power supply voltage provided to different sections of the TLB. Furthermore, the voltage or current of the CAM and reference signals generally vary independently of each other, i.e., they do not “track” each other. This is because in prior art TLBs the CAM and reference signals are typically generated by separate circuits having different transistor configurations. Under certain process or voltage conditions, the voltage or current relationship between the CAM signal and reference signal may change such that the match sense amplifier incorrectly senses a CAM row hit or miss. If this condition occurs, TLB
32
will not function properly and cannot be used. Therefore, the lack of tracking between the CAM signal and reference signal decreases the processing yield of the TLB.
Another problem experienced by prior art TLBs using pseudo-differential sensing is the difficulty in adjusting the voltage or current level of the reference signal. The reference signal is adjusted to place it in proper relation to the CAM signal level such that the match sense amplifier can correctly determine whether a CAM row hit or miss occurred. In prior art TLBs, the reference signal is typically adjustable through only a limited range of voltage or current levels. Furthermore, it is difficult to fine tune the voltage or current levels of the reference signal under varying process or voltage conditions because the reference signal adjustments may affect the tracking between the reference and CAM signals. If the reference signal level cannot be adjusted accurately, the match sense amplifier is susceptible to incorrectly sensing a CAM row hit or miss. Therefore, the difficulty in adjusting the reference signal level also decreases the processing yield of the TLB.
In view of the shortcomings of the prior art, it would be highly desirable to provide a TLB with a reference circuit that improves the processing yield of the TLB.
SUMMARY OF THE INVENTION
The present invention is a translation-lookaside buffer that includes a content-addressable memory (CAM) cell to generate a CAM current signal with a first transistor configuration having a set of transistors of a predetermined size and connection. A reference current circuit generates a reference current signal with a second transistor configuration corresponding to the first transistor configuration, with the exception of the size and connection of selected transistors. A match sense amplifier selectively generates a match signal in response to the CAM current signal and the reference current signal.
In one embodiment of the present invention, the reference current circuit comprises a reference current generator and a current limiting circuit, the current limiting circuit comprises a plurality of programmable transistors configurable in a predefined conducting state.
The translation-lookaside buffer of the present invention provides an improved yield in two ways: (1) the reference current circuit has a transistor configuration similar to that of the CAM cells so that the reference current signal tracks the signals gener
Chu Der-ren
Khieu Cong
Lee Lan
Liu Xin
Pennie & Edmonds LLP
Sun Microsystems Inc.
Thai Tuan V.
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