Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
2008-07-29
2008-07-29
Cao, Chun (Department: 2115)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
C713S323000, C712S234000
Reexamination Certificate
active
07406613
ABSTRACT:
In a pipelined processor, a pre-decoder in advance of an instruction cache calculates the branch target address (BTA) of PC-relative and absolute address branch instructions. The pre-decoder compares the BTA with the branch instruction address (BIA) to determine whether the target and instruction are in the same memory page. A branch target same page (BTSP) bit indicating this is written to the cache and associated with the instruction. When the branch is executed and evaluated as taken, a TLB access to check permission attributes for the BTA is suppressed if the BTA is in the same page as the BIA, as indicated by the BTSP bit. This reduces power consumption as the TLB access is suppressed and the BTA/BIA comparison is only performed once, when the branch instruction is first fetched. Additionally, the pre-decoder removes the BTA/BIA comparison from the BTA generation and selection critical path.
REFERENCES:
patent: 3800291 (1974-03-01), Cocke et al.
patent: 6591343 (2003-07-01), Col et al.
patent: 6678815 (2004-01-01), Mathews et al.
patent: 6735689 (2004-05-01), Thomson et al.
patent: 1304620 (2003-04-01), None
Kadayif et al, “Generating physical addresses directly for saving instruction TLB energy”, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, pp. 185-196, 2002.
Min et al, “A Selectively Accessing TLB for High Performance and Lower Power Consumption”, IEEE, pp. 45-48, 2002.
Lee et al, “Energy Efficient D-TLB and Date Cache using Semantic-Aware Multilateral Partitioning”, ISLPED 03, Aug. 25-27, 2003, Seoul, Korea.
Dieffenderfer James Norris
Sartorius Thomas Andrew
Smith Rodney Wayne
Stempel Brian Michael
Cao Chun
Ciccozzi John L.
Pauley Nicholas J.
Qualcomm Incorporated
Rouse Thomas
LandOfFree
Translation lookaside buffer (TLB) suppression for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Translation lookaside buffer (TLB) suppression for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Translation lookaside buffer (TLB) suppression for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2747702