Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2007-10-21
2010-10-05
Peugh, Brian R (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
Reexamination Certificate
active
07809922
ABSTRACT:
A node of a multiple-node system includes a translation lookaside buffer (TLB), a cache, and a TLB snoop mechanism. The node shares memory with other nodes of the multiple-node systems, and is connected with the other nodes via a bus. The TLB snooping mechanism snoops inbound memory access requests and/or outbound memory access requests. Inbound requests are received from over the bus and are intended for the cache. However, the cache receives only the inbound requests that relate to memory addresses having associated entries within the TLB. Outbound requests are received from within the node and are intended for transmission over the bus. However, the bus coherently transmits only the outbound requests that relate to memory addresses that are part of memory pages having set shared-memory page memory flags. All other outbound memory access requests are sent over the bus non-coherently.
REFERENCES:
patent: 4757447 (1988-07-01), Woffinden
patent: 6256715 (2001-07-01), Hansen
patent: 6633967 (2003-10-01), Duncan
patent: 2008/0320236 (2008-12-01), Ueda et al.
Tsuchiya Kenichi
Ueda Makoto
Dryja Michael
International Business Machines - Corporation
Peugh Brian R
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