Translation lookaside buffer prediction mechanism

Details Translation lookaside buffer prediction mechanism Translation lookaside buffer prediction mechanism

2006-09-27

2008-10-07

Nguyen, Hiep T (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S137000

Reexamination Certificate

active

07434027

ABSTRACT:
According to one embodiment a central processing unit (CPU) is disclosed. The CPU includes a translation lookaside buffer (TLB). The TLB predicts a set index value prior to the generation of an effective address.

REFERENCES:
patent: 5893930 (1999-04-01), Song

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