Translation look-aside buffer with look-up optimized for...

Details Translation look-aside buffer with look-up optimized for... Translation look-aside buffer with look-up optimized for...

2011-08-09

2011-08-09

Nguyen, Than (Department: 2188)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S207000, C711S149000

Reexamination Certificate

active

07996649

ABSTRACT:
A dual-port block random access memory (BRAM) can include first and second sections including direct mapped cache entries. The dual-port BRAM further can include third and fourth sections including translation look-aside buffer entries, wherein entries of the third section are associated with entries of the fourth section and wherein an entry of the third section and an associated entry of the fourth section collectively specify complete translation look-aside buffer data. The dual-port BRAM also can include first and second address ports concurrently accessing at least one of the first, second, third, or fourth sections of the dual-port BRAM to locate a virtual address to be translated.

REFERENCES:
patent: 5943284 (1999-08-01), Mizuno et al.
patent: 6484248 (2002-11-01), Wen
patent: 2002/0018359 (2002-02-01), Mizuno et al.

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