Translation look aside buffer (TLB) with increased...

Details Translation look aside buffer (TLB) with increased... Translation look aside buffer (TLB) with increased...

2006-08-15

2006-08-15

Portka, Gary (Department: 2188)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S206000

Reexamination Certificate

active

07093100

ABSTRACT:
Method and apparatus for increasing the number of real memory addresses accessible through a translational look-aside buffer (TLB) by a multi thread CPU. The buffer entries include a virtual address, a real address and a special mode bit indicating whether the address represents one of a plurality of threads being processed by the CPU. If the special mode bit is set, the real address associated with the virtual address higher order bits are concatenated with the thread identification number being processed to obtain a real address. Buffer entries containing no special mode bit, or special mode bit set to 0, are processed by using the full length of the real address associated with the virtual address stored in the look-aside buffer (TLB).

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