Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2006-05-24
2008-12-02
Lane, Jack A (Department: 2185)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S163000
Reexamination Certificate
active
07461232
ABSTRACT:
A translation look-aside buffer that stores address translations each of which associate a VPN with a PPN, and which are usable in a first mode of operation of a processor incorporating the buffer for accessing data stored in physical memory. Each entry in the buffer includes a first field for storing the VPN, a second field for storing an intermediate address portion IPN, and a third field for storing the PPN. The first field and the third field are mutually associated via the second field. The buffer is addressable in the first mode of operation of the processor by the content of the first fields. In response to a request for access to eternal memory, it outputs the PPN stored in the third field of a given entry when it is addressed by an input value corresponding to the VPN stored in the first field of said entry.
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Jorgenson Lisa K.
Lane Jack A
Seed IP Law Group PLLC
STMicroelectronics SA
Tarleton E. Russell
LandOfFree
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