Translation look aside buffer having separate RAM arrays which a

Details Translation look aside buffer having separate RAM arrays which a Translation look aside buffer having separate RAM arrays which a

1997-09-30

2000-06-20

Thai, Tuan V.

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

711104, 711205, 711207, 365 49, 36518905, G06F 1200

Patent

active

060789875

ABSTRACT:
A unified array access for two logically different arrays is provided. The first array includes CAM cells arranged in n rows and x columns. At least one CAM cell is coupled to a match line, a CAM word line, and to a CAM bit line. The second array includes first RAM cells arranged in n rows and y columns and second RAM cells arranged in n rows and z columns. At least one first RAM cell is coupled to a RAM word line, and to a first RAM bit line. At least one second RAM cell is coupled to the same RAM word line, and a second RAM bit line. RAM word line drivers are provided to activate the first and second RAM cells during a read or write access thereof. At least one RAM word driver has an output coupled to first and second RAM cells. N match sense amplifiers are provided, at least one of which has an input coupled to one of the CAM cells via a match line, and an output coupled to at least one RAM word driver. Y first RAM driver circuits are provided, at least one of which has a first output coupled to the first RAM bit line, a first input configured to receive a first data input signal, and a control input configured to receive a first RAM write enable signal. The first RAM write driver circuit is configured to charge the first RAM bit line in response to receiving the first RAM write enable signal. The second RAM write driver circuits are also provided, at least one of which has a second output coupled to the RAM bit line, a second input configured to receive a second data input signal, and a control input configured to receive a second RAM write enable signal. The second RAM write driver circuit is configured to charge the second RAM bit line in response to receiving the second write enable signal. Moreover, the second RAM write driver circuit is configured to operate independently from the first RAM write driver circuit.

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