Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
1998-11-13
2002-02-26
Bragdon, Reginald G. (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S156000, C711S122000, C711S128000
Reexamination Certificate
active
06351797
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to microprocessors and, more specifically, to a cache memory-based microprocessor that stores memory region configuration bits in a translation look-aside buffer (TLB).
BACKGROUND OF THE INVENTION
A cache memory is a small but very fast memory that holds a limited number of instructions and data for use by a processor. One of the most frequently employed techniques for increasing overall processor throughput is to minimize the number of cache misses. Another is to minimize the cache access time in a processor that implements a cache memory. The lower the cache access time, the faster the processor can run. Also, the lower the cache miss rate, the less often the processor is stalled while the requested data is retrieved from main memory and the higher is the processor throughput. There is a wealth of information describing cache memories and the general theory of operation of cache memories is widely understood. This is particularly true of cache memories implemented in x86 microprocessor architectures.
Many techniques have been employed to reduce the access time of cache memories. However, the cache access time is still limited by the rate at which data can be examined in, and retrieved from, the RAM circuits that are internal to a conventional cache memory. This is in part due to the rate at which address translation devices, such as the translation look-aside buffer (TLB), translate linear (or logical) memory addresses into physical memory addresses. If the TLB has a comparatively long access time for retrieving data, then the translation of the logical memory address into a physical address is comparatively slow. The slower this translation is, the slower the cache memory is in its overall operation.
Conventional personal computer (PC) architectures may specify selected areas of physical memory as having particular attributes with respect to reading and writing data. These attributes (or configuration data) are stored in dedicated registers that span the selected memory space. Thus, areas of physical memory may be set aside as non-cacheable, write protected, write back, weak locking, write gathering, cache-write-through, non-local bus, write-protect, read-protect or the like, regardless of how the operating system sets up the normal paging protections and definitions for those areas.
The region configuration data are used by very time critical control logic in a microprocessor to determine if data in the machine may be bypassed from stage to stage, or must instead be forced to execute in order, or in “serial” operation. Microprocessor performance greatly increases if data bypassing and data forwarding may be performed. However, if the region configuration data suffer any delay, it can reduce the operating frequency of the microprocessor. The two things that most directly determine overall microprocessor performance, namely instructions per cycle and clock frequency, are both aided by providing region configuration data as rapidly as possible.
The registers that specify the attributes of certain ranges of memory space are called address region registers, configuration control registers, region control registers, memory type region registers, or the like. During a memory access, these registers compare the physical address of the memory access to memory range values stored in the registers and, if there is a match, the attributes/configuration bits assigned to the memory range are forced upon that memory access.
Problems are encountered in using region control registers in this manner, however. Before the physical address of the memory access can be compared to the memory range values in the region control registers, the physical address must first be derived by translating the linear or logical address associated with the physical address. The address translation is time consuming and the translated physical address must then be applied the region control registers to fetch the region configuration data (i.e., attributes).
The end result is that the access time for retrieving region configuration data is lengthened, thereby delaying its arrival at the time critical control logic in the microprocessor that determines if certain data may be bypassed from stage to stage, or must instead be forced to execute in order, or in “serial” operation. This slows down data bypassing and data forwarding operations.
Therefore, there is a need in the art for improved cache memories that maximize processor throughput. There is a further need in the art for improved cache memories having a reduced access time. In particular, there is a need for improved cache memories that minimize cache latencies related to determining the region configuration bits associated with a memory location selected by a memory access operation.
SUMMARY OF THE INVENTION
The limitations inherent in the prior art described above are overcome by the present invention, which provides a translation look-aside buffer (TLB) that stores region configuration bits (or attribute bits) associated with each physical address stored in the TLB and that makes the region configuration bits available at the same time that the physical address is generated.
To accomplish this, the present invention requires that: 1) for each TLB entry, there are additional bits allocated for defining the region configuration bits for that page (i.e., non-cacheable, write-protect, write-back, etc.); 2) the TLB must always be enabled, whether or not paging is enabled; 3) during “table walks”—or when the TLB is not hit by a linear address—the region configuration bits are “looked up” or fetched during an extra clock cycle added to the table walk operation after the physical address has been determined (since table walks normally take many clock cycles, the additional cycle results in only minimal performance loss. There must be a minimal table walk for those addresses which are not mapped and which miss the TLB); and 4) the TLB must be flushed whenever region configuration bits are changed.
Accordingly, in an exemplary embodiment of the present invention, there is provided, for use in an x86-compatible processor having a physically-addressable cache, an address translation device for providing physical addresses to the cache, the address translation device comprising: 1) a tag array capable of storing received untranslated addresses in selected ones of N tag entries in the tag array; 2) a data array capable of storing translated physical addresses corresponding to the untranslated addresses in selected ones of N data entries in the data array; and 3) a region configuration array capable of storing region configuration bits associated with the translated physical addresses in selected ones of N region configuration entries in the region configuration array.
The term “array” as used herein, refers to a group of one or more physical storage cells in a memory, address translation device, buffer, register, or other processing unit that can store one or more data values.
According to one embodiment of the present invention, the address translation device is an L1 translation look-aside buffer providing physical addresses to a Level 1 cache.
According to another embodiment of the present invention, the L1 translation look-aside buffer is direct-mapped.
According to still another embodiment of the present invention, the address translation device is an L2 translation look-aside buffer providing physical addresses to a Level 2 cache.
According to yet another embodiment of the present invention, the L2 translation look-aside buffer is set-associative and comprises M ways.
According to a further embodiment of the present invention, the address translation device further comprises a flag array for storing mode flags corresponding to the translated physical addresses in selected ones of N flag entries in the flag array.
According to a still further embodiment of the present invention, the mode flags indicate whether the corresponding translated physical addresses were stored in the data a
Beard, Sr. Douglas R.
Bensley Darren
Green Daniel W.
Bragdon Reginald G.
Carr & Ferrell LLP
VIA-Cyrix Inc.
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