Translating loads for accelerating virtualized partition

Details Translating loads for accelerating virtualized partition Translating loads for accelerating virtualized partition

2007-01-23

2007-01-23

Verbrugge, Kevin (Department: 2189)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

Reexamination Certificate

active

11135838

ABSTRACT:
A system, which includes a processor that includes a plurality of cores, generates an address translation when there is a miss in a translation lookaside buffer (TLB). A hypervisor utilizes a translating load instruction that upon execution on the processor generates a data portion of a TLB entry. Execution of the translating load instruction utilizes information from a real-to-physical address translation table entry and information provided in the call to the translating load instruction to synthesize the data portion of a new virtual-to-physical translation table entry.

REFERENCES:
patent: 6742103 (2004-05-01), Chauvel et al.
patent: 6742104 (2004-05-01), Chauvel et al.
patent: 2002/0062434 (2002-05-01), Chauvel et al.
patent: 2002/0065989 (2002-05-01), Chauvel et al.
patent: 2005/0188175 (2005-08-01), Chiang et al.
patent: 2005/0188176 (2005-08-01), Chiang et al.

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