Translated memory protection apparatus for an advanced...

Electrical computers and digital processing systems: memory – Address formation – Address mapping

Reexamination Certificate

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C711S200000, C711S206000

Reexamination Certificate

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07840776

ABSTRACT:
A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.

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“Parallel Processing Mechansimȁ

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