Transitioning to and from a sleep state of a processor

Electrical computers and digital processing systems: support – Computer power control – Power conservation

Reexamination Certificate

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C713S323000

Reexamination Certificate

active

07870404

ABSTRACT:
A method for reducing power utilized by a processor including determining that a processor is transitioning from a computer mode to a mode in which system clock to the processor is disabled, and reducing core voltage to the processor to a value sufficient to maintain state during the mode in which system clock is disabled.

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