Transistor with vertical dielectric structure

Details Transistor with vertical dielectric structure Transistor with vertical dielectric structure

2006-03-28

2006-03-28

Lindsay, Jr., Walter L. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S212000, C438S283000

Reexamination Certificate

active

07018876

ABSTRACT:
A transistor (103) with a vertical structure (113) that includes a dielectric structure (201) below a semiconductor structure (109). The semiconductor structure includes a channel region (731) and source/drain regions (707, 709). The transistor includes a gate structure (705, 703) that has a portion laterally adjacent to the semiconductor structure and a portion laterally adjacent to the dielectric structure. In one embodiment, the gate structure is a floating gate structure wherein a control gate structure (719) also includes portion laterally adjacent to the dielectric structure and a portion laterally adjacent to the semiconductor structure. In some examples, having a portion of the floating gate and a portion of the control gate adjacent to the dielectric structure acts to increase the control gate to floating gate capacitance without significantly increasing the capacitance of the floating gate to channel region.

REFERENCES:
patent: 4648173 (1987-03-01), Malaviya
patent: 4859623 (1989-08-01), Busta
patent: 5689127 (1997-11-01), Chu et al.
patent: 5804848 (1998-09-01), Mukai
patent: 6011725 (2000-01-01), Eitan
patent: 6097065 (2000-08-01), Forbes et al.
patent: 6150687 (2000-11-01), Noble et al.
patent: 6300182 (2001-10-01), Yu
patent: 6330184 (2001-12-01), White et al.
patent: 6355961 (2002-03-01), Forbes
patent: 6372559 (2002-04-01), Crowder et al.
patent: 6396108 (2002-05-01), Krivokapic et al.
patent: 6413802 (2002-07-01), Hu et al.
patent: 6414356 (2002-07-01), Forbes et al.
patent: 6433609 (2002-08-01), Voldman
patent: 6458662 (2002-10-01), Yu
patent: 6472258 (2002-10-01), Adkisson et al.
patent: 6583469 (2003-06-01), Fried et al.
patent: 6657252 (2003-12-01), Fried et al.
patent: 6855588 (2005-02-01), Liao et al.
patent: 2003/0113970 (2003-06-01), Fried et al.
patent: 2003/0178670 (2003-09-01), Fried et al.
patent: 101 25 967 (2001-05-01), None
patent: WO 00/021118 (2000-04-01), None
Related U.S. Appl. No. 10/074,732 entitled “Method of Forming a Vertical Double Gate Semiconductor Device and Structure Thereof” filed Sep. 3, 2002.
Related U.S. Appl. No. 10/443,375 entitled “Transistor With Independent Gate Structures” filed May 22, 2003.
Related U.S. Appl. No. 10/443,908 entitled “Memory with Charge Storage Locations” filed May 22, 2003.
Related U.S. Appl. No. 10/427,141 entitled “Semiconductor Fabrication Process with Asymmetrical Conductive Spacers” filed Apr. 30, 2003.
Related U.S. Appl. No. 10/324,787 entitled “Vertical MOSFET with Asymmetric Gate Structure,” filed Dec. 20, 2002.
Lee et al.; “Multilevel Vertical-Channel SONOS Nonvolatile Memory on SOI”; IEEE Electron Device Letters, 2002; pp 1-3 and 208-209.
Yu, Bin et al; FinFET Scaling to 10nm Gate Length:; IEEE IDEM 2002; pp 251-254; IEEE.
Choi, Yang-Kyu et al.; “Sub-20nm CMOS FinFET Technologies”; 2001 IEEE, 4 pp.
Kedzierski, Jakub et al.; “High-Performance Symmetric-Gate and CMOS-Compatible Vt Asymmetric-Gate FinFET Devices”; 2001; IEEE; 4 pp.
Kim, Keunwoo et al.; “Double-Gate CMOS Symmetrical—Versus Asymmetrical-Gate Devices”; IEEE Transactions On Electron Devices, vol. 48, No. 2; Feb. 2001; pp 294-299.
Fossum, Jerry G. et al.; “Extraordinarily High Drive Currents in Asymmetrical Double-Gate MOSFETS”; Superlattices and Microstructures, vol. 28, No. 5/6, 2000, 2000 Academic Press, pp 525-530.
Hisamoto, Digh et al.; “FinFET—A Self-Aligned Double-Gate MOSFET Scalable to 20 nm”; IEEE Transactions on Electron Devices; vol. 47, No. 12, Dec. 2000, pp 2320-2325.
Tanaka, Tetsu et al; Ultrafast Operation of Vth-Adjustedp+n+Double Gate SOI MOSFET's; IEEE Electron Device Letters, vol. 15, No. 10, Oct. 1994; pp. 386-388.
Chan et al.; “A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device”; IEEE Electron Device Letters; Mar. 1987; pp 93-95; vol. EDL-8, No. 3.
Gonzalez, Fernando Sr. et al.; “A Dynamic Source-Drain Extension (DSDE) MOSFET Using a Separately Biased Conductive Spacer”; pp 645-648.
Singer, Peter, “Duel Gate Control Provides Treashold Voltage Options,” Semiconductor International, Nov. 1, 2003, 2 pgs.

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