Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-04-16
2004-03-16
Nelms, David (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S548000, C257S549000, C257S550000, C438S223000, C438S224000, C438S227000, C438S228000
Reexamination Certificate
active
06707115
ABSTRACT:
BACKGROUND
The present invention relates to a transistor that is resistant to hot electron injection.
In the quest to add functionality while cutting the price of integrated circuits (ICs), process and device technology have been developed to improve the performance of the ICs. These ICs' fundamental building blocks include transistors. One approach to improve performance involves scaling down the physical dimensions of transistors. Scaling down the physical dimensions increases the number of individual transistors that can be placed onto a single silicon chip or die. More transistors on a single chip lead to increased functionality. Also, since scaled down transistors are close to each other, scaling down the dimensions can result in improved performance, and particularly the speed, of the transistors.
A typical transistor such as a metal-oxide semiconductor field-effect transistor (MOSFET) uses a gate to control an underlying surface channel joining a source and a drain. The channel, source and drain are located in a semiconductor substrate, with the source and drain being doped oppositely to the substrate. The gate is separated from the semiconductor substrate by an insulating layer such as a gate oxide. The operation of the transistor involves applying an input voltage to the gate to set up a transverse electric field in the channel in order to modulate the longitudinal conductance of the channel.
One method to increase the speed of a transistor is to reduce the length of the conduction channel underneath the gate and gate oxide regions. For example, MOSFET devices have been scaled to the point where the channel length from source to drain falls below 0.18 micron (deep submicron). As the channel shrinks, the maximum electric field (E-field) in the channel region increases, thereby resulting in higher substrate current and short/long term hot electron reliability problems. Electrons traveling through the channel become more energized by the E-field and have a greater tendency to cross into the gate region and become trapped. The short channel lengths involved in such scaled down transistors have involved limitations from the electrical characteristics present in such scaled down devices. The limitations on such short channel device have included limited drain voltage, threshold voltage (V
T
) falloff, and impact ionization in the drain pinchoff region. The drain voltage is limited by punch-through, snap back and gate field enhanced P-N junction avalanche breakdown. The threshold voltage falloff is caused by the drain field induced barrier lowering and the drain and poor control over source junction doping profile and substrate doping concentration. As transistor dimensions are reduced and the supply voltage remains constant, the electric field in the channel near the drain tends to increase. If the electric field becomes strong enough, it can give rise to so-called hot-carrier effects. For instance, hot electrons can overcome the potential energy barrier between the substrate and the gate insulator thereby causing hot carriers to become injected into the gate insulator. Thus, the impact ionization in the drain pinchoff region leads to hot-electron injection into the gate oxide as well as hot-electron injection into the substrate. Trapped charge in the gate insulator due to injected hot carriers accumulates over time and can lead to a permanent change in the threshold voltage of the device. Thus, a point exists where heightened speed and reduced dimensions leads to transistor breakdown.
Also, the hot electrons can travel long distances in the semiconductor substrate, eventually reaching areas with low noise circuitry where they can substantially increase the noise floor. Such low noise circuits include, among others, CMOS imagers, high resolution analog to digital converters and digital to analog converters, and radio frequency low noise amplifiers. These problems are particularly acute in mixed mode circuits with a combination of digital and analog circuitry.
Various methods have been employed to partially overcome these problems and maximize performance and reliability. One common method involves adding a first lightly doped region between the drain and channel regions and a second lightly doped region between the source and channel regions. After patterning the polysilicon gate, a low dosage phosphorous implant and a high temperature drive is used to create N− regions adjacent to the gate. After formation of the insulating sidewall spacer structures, a high dosage arsenic implant and drive can be used to create N+ source and drain regions which supersede most of the lightly doped N− regions. What remains are lightly doped regions separating the source and drain from the channel. This structure has come to be known as a lightly doped drain (LDD) structure.
The use of LDD structures to relax the E-field is well known, as discussed in U.S. Pat. No. 6,159,813. However, as the devices get smaller, and FET channels become shorter than 0.4 microns, limitations on fabrication precision result in structures that are far from ideal. Due to its high diffusivity, the phosphorous in the N− regions further diffuses into the channel during the high heat drive processes required to create the N+ source and drain regions. An alternative to the phosphorous LDD (phos-LDD) approach is to use arsenic to create the LDD structures. The fabrication processes required to create an arsenic LDD (As-LDD) proceed similarly to the phosphorous LDD processes. The LDD structure can be created by first implanting a low dosage, self-aligned arsenic implant prior to sidewall spacer formation. This implant is then diffused into the substrate through a heating drive process, resulting in the lightly doped N− regions. Arsenic's low diffusivity can cause the LDD regions to have an abrupt end below the edges of the gate region. This abruptness creates an E-field that is still unsuitable in sub half-micron devices due to the resulting hot electron reliability problem. Another method to reduce the E-field involves burying the drain/channel and source/channel junctions. The transistor includes N+ source and drain regions each having a projection that exists a distance below the channel/gate dielectric material layer. This moves the highest concentration of hot-electrons deeper into the channel area and away from the gate dielectric region. Buried structures incorporating LDD regions and graded combination structures have also been created, but at the expense of device speed. Although these structures reduce the hot electron problem, they can be costly to fabricate. Finally, most of the methods used to prevent hot electron effects also increase the series resistance of the transistor, since they introduce a high resistance, lowly doped region between the drain and source electrodes and the gate channel. This region limits the voltage reaching the channel through voltage (I*R) drops.
SUMMARY
In one aspect, a device includes a layer of gate oxide on a surface of the semiconductor substrate; a gate electrode formed on the surface of the gate oxide, the gate electrode having a drain side; a p-well implanted within a semiconductor substrate under the gate electrode; an n-well implanted in the p-well on the drain side; an n+ source region in the p-well outside of the n-well; an n+ drain region within the substrate inside the n-well; and lightly doped regions extending respectively from the source and drain regions toward the gate electrode.
Implementations of the device may include one or more of the following. The n-well extends slightly under the gate electrode. The p-well is deeper than the n-well. A second device can be fabricated adjacent the first device with a second gate electrode formed on the surface of the gate oxide; a second n-well implanted within a semiconductor substrate under the second gate electrode; a p+ source region in the second n-well; and a p+ drain region within the substrate inside the second n-well. The second n-well is adjac
AirIP Corporation
Ho Tu-Tu
Nelms David
Tran B.
Tran & Associates
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