Transistor with low resistance metal source and drain vertically

Details Transistor with low resistance metal source and drain vertically Transistor with low resistance metal source and drain vertically

1999-01-06

2000-05-02

Saadat, Mahshid

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257330, 257408, 257751, 257902, H01L 2976

Patent

active

060575832

ABSTRACT:
A transistor is provided and formed using self-aligned low-resistance source and drain regions within a metal-oxide semiconductor (MOS) process. The gate of the transistor may also be formed from a low-resistance material such as a metal. The source and drain regions of the transistor are configured upon a semiconductor substrate, and the transistor channel is within the substrate. A protective dielectric layer is deposited over the semiconductor substrate. Source/drain trenches are formed in the protective dielectric layer and subsequently filled with sacrificial dielectrics. The protective dielectric lying between these sacrificial dielectrics is removed, and replaced with sidewall spacers, a gate dielectric, and a gate conductor which may be formed from a low-resistance metal. The sacrificial dielectrics are subsequently removed and replaced with source/drain regions which are preferably formed from a low-resistance metal. The resulting transistor may exhibit low contact and series resistances, and increased operating speed.

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Kimura et.al. "Short Effect Suppresed Sub 0.1 microns Grooved Gate MOSFET with W Gate", IEEE Transactions, Jan. 1995.

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