Active solid-state devices (e.g. – transistors – solid-state diode – Including semiconductor material other than silicon or...
Reexamination Certificate
2000-02-29
2003-01-14
Fahmy, Wael (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Including semiconductor material other than silicon or...
C257S019000, C257S055000, C257S063000, C257S613000, C257S616000
Reexamination Certificate
active
06507091
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority from prior French Patent Application No. 99-02513, filed Mar. 1, 1999, the entire disclosure of which is herein incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to transistors, and more specifically to a transistor having indium implanted into an SiGe alloy and a process for fabricating such a transistor.
2. Description of Related Art
One conventional technique for adjusting the threshold voltage of a conventional silicon transistor in order to improve its performance characteristics is to implant heavy ions, such as indium and arsenic, into the silicon channel of the transistor. These dopants make it possible to better control the drop in threshold voltage when the dimensions of the transistor decrease (the short-channel effect), and the degradation of the below-the-threshold slope. In addition, indium provides other advantageous effects with regard to the variation of the threshold voltage in long transistors (usually this voltage does not vary in long transistors).
The implantation of indium into the silicon of the channel initially has an advantageous retrograde profile. However, during subsequent heat treatments that are required to fabricate the transistor, the implanted indium diffuses so as to degrade the initial retrograde profile. Furthermore, in the fabricated transistor, the indium becomes electrically active in the silicon poorly. In other words, the profile of the electrically active implanted indium is substantially different from the chemical profile of the indium implantation.
SUMMARY OF THE INVENTION
In view of these drawbacks, it is an object of the present invention to overcome the above-mentioned drawbacks and to provide an indium-implanted transistor that has improved characteristics as compared with conventional transistors. Such characteristics can include the threshold voltage (V
th
), the below-the-threshold slope (S), the short-channel effect (SCE), and/or the drain-induced barrier lowering (DIBL).
Another object of the present invention is to provide an indium-implanted transistor having a retrograde stable implanted indium profile that is similar to the initial chemical profile of the implanted indium.
Yet another object of the present invention is to provide a process for fabricating an indium-implanted transistor with improved characteristics.
One embodiment of the present invention provides an indium-implanted transistor having a silicon channel region that includes a buried layer of an Si
1−x
Ge
x
alloy into which indium is implanted, with 10
−5
≦x≦4×10
−1
. In a preferred embodiment, 10
−4
≦x≦10
−1
, and the implanted indium is in the range of from 1×10
11
to 4×10
15
atoms/cm
2
.
Another embodiment of the present invention provides a first method for fabricating an indium-implanted transistor. According to the first method, a multilayer composite film is produced on at least one region of a surface of a silicon substrate where a channel region of the transistor is to be formed. The multilayer composite film includes at least one Si
1−x
Ge
x
alloy layer, in which 10
−5
≦x≦4×10
−1
, and an external silicon layer. Indium is implanted into the Si
1−x
Ge
x
alloy layer, and fabrication of the transistor is completed so as to produce the transistor with a channel region that includes a buried Si
1−x
Ge
x
alloy layer into which the indium is implanted. In one preferred method, the multilayer composite film is a three-layer film that includes a silicon layer between the surface of the substrate and the Si
1−x
Ge
x
alloy layer.
Yet another embodiment of the present invention provides a second method for fabricating an indium-implanted transistor. According to the second method, germanium is implanted into at least one region of a silicon substrate where a channel region of a transistor is to be formed, in order to form a buried layer of an Si
1−x
Ge
x
alloy in which 10
−5
≦x≦4×10
−1
. Indium is implanted into the Si
1−x
Ge
x
alloy layer, and fabrication of the transistor is completed so as to produce the transistor with a channel region that includes a buried Si
1−x
Ge
x
alloy layer into which the indium is implanted. In one preferred method, the implanted germanium is in the range of from 10
12
to 10
16
atoms/cm
2
, and the germanium implantation energy is from 20 to 300 keV.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the present invention, are given by way of illustration only and various modifications may naturally be performed without deviating from the present invention.
REFERENCES:
patent: 5272365 (1993-12-01), Nakagawa
patent: WO97/23000 (1997-06-01), None
P. Bouillon et al., “Re-examination of Indium Implantation for a Low Power O. 1 &mgr;m Technology” Technical Digest of the International Electron Devices Meeting (IEDM), Dec. 10-13, 1995, pp. 897-900, XP000624815.
P. Bouillon et al., “Anomalous Short Channel Effects in Indium Implanted nMOSETs”, International Electron Devices Meeting 1997, IEDM Technical Digest, Dec. 7-20, 1997, pp. 231-234, XP002118637.
Preliminary Search Report dated Oct. 13, 1999 with annex on French Application No. 99/02513.
Alieu Jérôme
Skotnicki Thomas
Bongini Stephen
Fahmy Wael
Jorgenson Lisa K.
Soward Ida M.
STMicroelectronics S.A.
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