Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – Plural fluid growth steps with intervening diverse operation
Reexamination Certificate
2002-08-13
2004-01-13
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
Plural fluid growth steps with intervening diverse operation
C438S443000, C438S451000
Reexamination Certificate
active
06677223
ABSTRACT:
CROSS-REFERENCES TO RELATED APPLICATIONS
This application claims priority from R.O.C. Patent Application No. 090123295, filed Sep. 21, 2001, the entire disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to semiconductor manufacturing and, more particularly, to improving the uniformity of substrate impurity concentration, which may be used to form a transistor with a highly uniform threshold voltage.
Threshold voltages of transistors are seriously affected by the impurity concentration of the substrate on which the transistors are formed. A low uniformity of substrate impurity concentration causes a huge variation of the threshold voltages of the transistors formed on a single wafer.
The impurity concentration uniformity of the substrate deteriorates easily, for instance, during P-body driving in and formation of SAC (sacrificial) oxide layers. In the two processing steps, the wafer or substrate is disposed in an oxygen gas at a temperature of 900° C. and heated to 1100° C. at a rate of 5° C./min. The wafer is distorted due to the differences between expansion coefficients of layers on the wafer, whereby the lattice of the silicon substrate is enlarged in some areas on the wafer. This causes the oxygen to diffuse into the substrate and decreases the impurity concentration in those areas. Therefore, the impurity concentration of the substrate is non-uniform, which can result in a significant variation of the threshold voltages of the transistors subsequently formed on the substrate.
BRIEF SUMMARY OF THE INVENTION
Embodiments of the present invention relate to processes utilized in the manufacturing of a semiconductor device having transistors to achieve high uniformity of threshold voltages. The invention does so by ensuring high uniformity of impurity concentration in the substrate. During P-body driving in by heating the substrate and the source of impurities from a first initial temperature to a first target temperature in an oxygen gas, the initial temperature is set sufficiently low to prevent the oxygen from diffusing into the substrate and decrease the impurity concentration. During the formation of SAC oxide layer by heating the substrate from a second initial temperature to a second target temperature in an oxygen gas, the rate of increasing the temperature is set sufficiently high to achieve rapid formation of the oxide layer on the substrate so as to prevent the impurities driven into the substrate from diffusing out of the substrate.
In accordance with an aspect of the present invention, a method for manufacturing a semiconductor device having transistors with high uniformity of threshold voltages comprises providing a substrate and a source of impurities, and disposing the substrate and the source of impurities in a first oxygen gas at a first initial temperature and heated to a first target temperature at a first temperature rate to drive the impurities into the substrate. The first initial temperature is sufficiently low to prevent the oxygen from diffusing into the substrate. The substrate is disposed in a second oxygen gas at a second initial temperature and heated to a second target temperature at a second rate to form an oxide layer on the substrate. The second rate is high enough for rapid formation of the oxide layer on the substrate so as to prevent the impurities driven into the substrate from diffusing out from the substrate.
In some embodiments, the substrate is a silicon substrate. The first initial temperature ranges from about 750° C. to about 850° C. The first rate ranges from about 4° C./min to about 6° C./min. The first target temperature is about 1100° C. The second initial temperature ranges from about 850° C. to about 950° C. The second rate ranges from about 8° C./min to about 12° C./min. The method may further comprise forming a trench in the substrate wherein the oxide layer is formed along sidewalls of the trench. A conducting layer may be formed on the oxide layer, filling the trench.
In specific embodiments, the second target temperature is about 1100° C. A conducting layer may be formed on the oxide layer. The conducting layer is a polysilicon layer. The oxide layer is a sacrificial oxide layer.
In accordance with another aspect of the present invention, a method for manufacturing a semiconductor device comprises providing a substrate and a source of impurities, and disposing the substrate and the source of impurities in a first oxygen gas at a first initial temperature and heated to a first target temperature at a first temperature rate to drive the impurities into the substrate. The first initial temperature is sufficiently low to prevent the oxygen from diffusing into the substrate.
In some embodiments, the first initial temperature is substantially below 900° C. The first initial temperature typically ranges from about 750° C. to about 850° C.
In accordance with another aspect of the invention, a method of forming an oxide layer on a substrate containing impurities comprises disposing the substrate containing the impurities in a second oxygen gas at a second initial temperature and heated to a second target temperature at a second rate to form an oxide layer on the substrate. The second rate is high enough for rapid formation of the oxide layer on the substrate so as to prevent the impurities driven into the substrate from diffusing out from the substrate.
In some embodiments, the second initial temperature ranges from about 850° C. to about 950° C., and the second target temperature is about 1100° C. The second rate is substantially greater than 5° C./min. The second rate typically ranges from about 8° C./min to about 12° C./min.
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patent: 6559518 (2003-05-01), Niwa
Chang Chien-Ping
Chuang Chiao-Shun
Hsieh Hsin-Huang
Tseng Mao-Song
Lindsay Jr. Walter L.
Mosel Vitelic Inc.
Niebling John F.
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