Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-03-21
2004-06-15
Kielin, Erik (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S591000
Reexamination Certificate
active
06750501
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile storage element, particularly to a transistor type ferroelectric nonvolatile storage element using a ferroelectric body for a gate thereof and a method of fabricating the same.
2. Description of the Related Art
As a transistor type ferroelectric nonvolatile storage element, there is MFS-FET(Metal-Ferroelectric-Semiconductor-Field Effect Transistor: conductor film-ferroelectric film-semiconductor-field effect type transistor) having a construction in which an oxide film constituting an insulating film of normal MOS-FET(Metal Oxide Semiconductor-Field Effect transistor: conductor film-oxide film-semiconductor-field effect transistor) as a basic structure thereof. The MFS-FET type memory is of a type in which polarization of a ferroelectric body changes threshold voltage of the transistor and a change in resistance of a channel between a source and a drain is read as a change in large or small of a drain current value. This type is characterized by nondestructive reading in which information is not destructed by a reading operation at low voltage since ON/OFF of the transistor is maintained by holding residual polarization of the ferroelectric body.
According to MFS-FET arranged with a ferroelectric body at its gate, it is difficult to produce an excellent interface between the ferroelectric body (F) and the semiconductor (S). A method of avoiding the difficulty is classified into two kinds in gross classification. According to one of the methods, in a ferroelectric transistor having a structure of MFIS (Metal -Ferroelectric-Insulator-Semiconductor: conductor film -ferroelectric body film-insulator film-semiconductor), an insulating film (I) is sandwiched between the ferroelectric body film (F) and the semiconductor (S) of an MFS structure. The ferroelectric body induces electric charge on a surface of a semiconductor substrate via a gate insulating film by polarization thereof.
According to other of the methods, in a ferroelectric body having a structure of MFMIS (Metal-Ferroelectric-Metal -Insulator-Semiconductor: conductor film-ferroelectric film-conductor film-insulating film-semiconductor), a conductor film (M) (or referred to as floating gate) is sandwiched between the ferroelectric body film (F) and the insulating film (I) of the MFIS structure. The invention relates to latter of the MFMIS structure.
Further, a conductor film or a conductor layer described in the specification, includes a metal as well as a conductor of polycrystal silicon, or an alloy of a metal and polycrystal silicon or the like.
According to a conventional MFMIS type ferroelectric memory, as shown by
FIG. 4A
, a source region
42
and a drain region
43
are formed on a semiconductor substrate
41
, at a main face of the semiconductor substrate therebetween, there are laminated an oxide film (SiO
2
)
44
constituting a gate oxide film and polysilicon (Poly-Si)
45
constituting a lower conductor film, there is laminated Ir/IrO
2
(iridium/iridium oxide) constituting a barrier film
46
constituting the lower conductor film and for preventing mutual diffusion between a ferroelectric body material and Poly-Si further thereabove, there is laminated a ferroelectric body thin film (for example, PZT (PbZr
X
Ti
1−X
O
3
) )
47
thereabove and there is laminated an upper conductor film
48
, that is, Ir/IrO
2
constituting a gate electrode thereabove. A gate structure
49
is formed by subjecting the laminated films to lithography and etching. (Reference: T Nakamura et al. Dig. Tech. Pap. of 1995 I EEE Int. Solid State Circuits Conf. p.68 (1995))
FIG. 4B
represents the MFMIS structure of
FIG. 4A
by an equivalent circuit and capacitance (C
F
) of a ferroelectric body capacitor comprising the upper MFM structure and capacitance (C
I
) of a gate insulator capacitor comprising the lower MIS structure, are connected in series. In
FIG. 4B
, when voltage is applied between the upper electrode A and the semiconductor substrate B to thereby polarize the ferroelectric layer, it is necessary from a view point of a memory holding characteristic to apply the voltage to sufficiently saturate polarization of the ferroelectric body.
Voltage distributed to the ferroelectric capacitor, is dependent on a coupling ratio (C
I
/(C
I
+C
F
)) of the capacitance (C
F
) of the ferroelectric capacitor and the capacitance (C
I
) of the gate insulator capacitor.
In order to increase the voltage distributed to the ferroelectric capacitor, it is important to design such that the capacitance (C
I
) of the gate insulator capacitor becomes larger than the capacitance (C
F
) of the ferroelectric body capacitor.
Hence, it is conceivable to thin the gate insulating film and thicken the ferroelectric thin film in order to design such that the capacitance (C
I
) of the gate insulator capacitor becomes larger than the capacitance (C
F
) of the ferroelectric capacitor, however, there is a limit in thinning the gate insulator film
44
in view of withstand voltage and leakage current. Further, when the ferroelectric body thin film
47
is thickened, in order to saturate polarization of the ferroelectric body, high drive voltage is needed.
A conventional method of making the capacitance (C
I
) of the gate insulator capacitor larger than the capacitance (C
F
) of the ferroelectric capacitor by avoiding these problems, is a method of changing areas of the capacitance (C
F
) and the capacitance (C
I
)
FIG. 4C
shows a simple schematic sectional view of carrying out the method. There is provided an MFMIS structure having the ferroelectric layer at only a portion of an area of the MIS (conductive body-insulator-semiconductor) portion for constituting C
I
. By the conventional method, C
I
can be designed to be larger than C
F
as necessary.
The conventional structure as shown by
FIG. 4A
poses a problem that after forming the MFMI structure (gate structure
49
) by the same dimensions, when impurities are introduced to the source region
42
and the drain region
43
and a heat treatment such as activation is carried out, impurities included in the ferroelectric body are extricated and diffused to silicon to thereby deteriorate the device characteristic.
Further, when an end face of the MFMI structure is summarizingly machined as in
FIG. 4A
, damage is caused at a sidewall thereof and therefore, a leakage path is formed. The leakage path is formed in, for example, dry etching, by adhering an electrode material (conductor material) scraped off in etching and a formed product (conductive) of a resist to the sidewall of the ferroelectric body. When the leakage path is formed, leakage current is conducted to the leakage path, electric charge is accumulated at the lower conductor film (polysilicon film
45
, barrier film
46
) of the MFMI structure and electric line of force from the ferroelectric film
47
are blocked. As a result, there poses a problem that carriers on the surface of the semiconductor substrate
41
are extinguished, although polarization remains, drain current is prevented from flowing and stored information is extinguished.
Meanwhile, even in the conventional structure in which the area of the upper conductor film of the MFMI structure is made to be smaller than the area of the lower structure in order to make the capacitance (C
I
) of the gate insulator capacitor lager than the capacitance (C
F
) of the ferroelectric capacitor as shown by
FIG. 4C
, after machining the respective films similarly by lithography and etching, when impurities are introduced to the source region
42
and the drain region
43
and a heat treatment such as activation or the like is carried out, impurities included in the ferroelectric body are extricated and diffused to the silicon to thereby pose the problem of deteriorating the device characteristic and cause damage to the side wall and therefore, the leakage path is formed. When the leakage path is formed, leakage current is conducted to the leakage path, electric charge is accumulated at th
Sakamaki Kazuo
Tarui Yasuo
Jordan and Hamburg LLP
Kielin Erik
Tarui Yasuo
LandOfFree
Transistor type ferroelectric body nonvolatile storage element does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Transistor type ferroelectric body nonvolatile storage element, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Transistor type ferroelectric body nonvolatile storage element will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3306621