Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-04-21
2002-07-23
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S317000
Reexamination Certificate
active
06424002
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to transistors, transistor arrays and non-volatile semiconductor memories.
2. Description of the Background Art
In recent years, non-volatile semiconductor memories such as Ferro-electric Random Access Memory, EPROM (Erasable and Programmable Read Only Memory), EEPROM (Electrically Erasable and Programmable Read Only Memory) have attracted much attention. In the EPROM or EEPROM, data is stored by storing charge at the floating gate and detecting a change in the threshold voltage based on the presence/absence of charge by a control gate. Such EEPROM includes a flash EEPROM which erases data for the entire memory chip or erases data on the basis of each of arbitrary blocks formed by dividing a memory cell array.
The flash EEPROM has increasing applicabilities such as for a memory for storing programs or data in a mobile telephone or a mobile information terminal for its advantages including: (1) stored data is non-volatile, (2) power consumption is low, (3) data can be electrically rewritten (rewritten on board), (4) the cost is low.
Memory cells forming the flash EEPROM include split-gate or stacked-gate type memory cells.
In flash EEPROM with the stacked-gate type memory cells, if charge is excessively pulled out from the floating gate electrode at the time of erasing data, the channel region attains an on state even if a prescribed voltage (0 V, for example) to drive a memory cell into an off state is applied to the control gate electrode. As a result, the memory cell continuously attains an on state, which disables reading of stored data, in other words, so-called over-erasure is caused. In order to prevent the over-erasure, the procedure of erasure must be devised, the procedure of erasure should be controlled, for example, by a peripheral circuit of the memory device, or by an external circuit.
The split-gate type memory cell was developed to prevent such over-erasure experienced in the stacked-gate type memory cell.
A flash EEPROM using a split-gate type memory cell is disclosed by WO92/18980.
FIG. 15
is a cross sectional view of a conventional split-gate memory cell
201
.
Split-gate type memory cell (split-gate type transistor)
201
includes a source region
203
, a drain region
204
, a channel region
205
, a floating gate electrode
206
, and a control gate electrode
207
.
N type source region
203
and drain region
204
are formed on a P type monocrystalline silicon substrate
202
. Floating gate electrode
206
is formed on channel region
205
between source region
203
and drain region
204
with a gate insulating film
208
interposed therebetween. Control gate electrode
207
is formed on floating gate electrode
206
with an insulating film
209
and a tunnel insulating film
210
interposed therebetween. Insulating films
209
and
210
are formed by means of LOCOS (Local Oxidation of Silicon). Insulating film
209
forms raised portions
206
a
at both corners on the upper part of floating gate electrode
206
.
Herein, a part of control gate electrode
207
is disposed on channel region
205
with insulating films
208
and
210
interposed therebetween to form a select gate
211
. Select gate
211
, source region
203
and drain region
204
form a select transistor
212
. More specifically, split-gate type memory cell
201
includes a series-connection of a transistor and select transistor
212
formed of gate electrodes
206
and
207
and regions
203
and
204
.
FIG. 16A
is a partial cross sectional view of a memory cell array
302
in a flash EEPROM
301
using split-gate type memory cell
201
.
Memory cell array
302
includes a plurality of memory cells
201
formed on P-type monocrystalline silicon substrate
202
.
Two memory cells
201
(hereinafter also separately referred to as “
201
a
” and “
201
b
”) commonly use source region
203
for the purpose of reducing the area occupied by the memory cells on substrate
202
, and floating gate electrode
206
and control gate
207
are disposed in an inverted manner to common source region
203
.
FIG. 16B
is a partial plan view of memory cell array
302
.
FIG. 16A
is a cross sectional view taken along line X—X in FIG.
16
B.
A field insulating film
213
is formed on substrate
202
, and isolates memory cells. Source region
203
is common to memory cells
201
a
and
201
b
provided the longitudinal direction of FIG.
16
B. Control gate electrode
207
is common to memory cells
201
a
and
201
b
disposed in the longitudinal direction of
FIG. 16B
, and control gate
207
forms a word line. Each drain region
204
disposed in the transverse direction of
FIG. 16B
is connected to a bit line (not shown) through a bit line contact
214
.
FIG. 17
shows a general configuration of flash EEPROM
301
using split-gate type memory cell
201
.
Memory cell array
302
includes a plurality of memory cells
201
formed in a matrix. The control gate electrodes
207
of memory cells
201
arranged in the row-direction form common word lines WL
1
to WLn. The drain regions
204
of memory cells
201
arranged in the column-direction are connected to common bit lines BL
1
to BLn.
Memory cells-
201
b
connected to odd-numbered word lines (WL
1
, WL
3
, . . . , WLm, . . . , WLn−1) and memory cells
201
a
connected to even-numbered word lines (WL
2
, WL
4
, WLm+1, . . . , WLn) respectively commonly use source regions
203
, and common source regions
203
form source lines RSL
1
, . . . , RSLm, . . . , RSLn. Each memory cell
201
b
connected to word line WLm and each memory cell
201
a
connected to word line WLm+1, for example, commonly use source region
203
, and the common source region
203
forms source line RSLm. Source lines RSL
1
to RSLn are connected to a common source line SL.
Word lines WL
1
to WLn are connected to a row decoder
303
, and bit lines BL
1
to BLn are connected to a column decoder
304
.
A row address and a column address externally specified are input to an address pin
305
. The row address and column address are transferred to an address latch
307
from address pin
305
. Among the addresses latched at address latch
307
, the row address is transferred to row decoder
303
through an address buffer
306
, and the column address is transferred to column decoder
304
through the address buffer
306
.
Row decoder
303
selects one of word lines WL
1
to WLn (WLm, for example) corresponding to the row address latched at address latch
307
, and controls the potential of each of word lines WL
1
to WLn according to each operation mode which will be described. More specifically, by controlling the potential of each of word lines WL
1
to WLn, the potential of the control gate electrode
207
of each memory cell
201
is controlled.
Column decoder
304
selects one of bit lines BL
1
to BLn (BLm, for example) corresponding to the column address latched at address latch
307
, and controls the potential of each of bit lines BL
1
to BLn corresponding to each operation mode. More specifically, by controlling the potential of each of bit lines BL
1
to BLn, the potential of the drain region
204
of each memory cell
201
is controlled.
Common source line SL is connected to a source line bias circuit
312
. Source line bias circuit
312
controls the potential of each of source lines RSL
1
to RSLn through common source line SL according to each operation mode. More specifically, by controlling the potential of each of source lines RSL
1
to RSLn, the potential of the source region
203
of each memory cell
201
is controlled.
Externally specified data is input to data pin
308
. The data is transferred to column decoder
304
through an input buffer
309
from data pin
308
. Column decoder
304
controls the potential of each of bit lines BL
1
to BLn based on the data as will be described later.
Data read out from an arbitrary memory cell
201
is transferred to a sense amplifier
310
through column decoder
304
from a corresponding one of bit lines BL
1
to BLn. Sense amplifie
Fujiwara Hideaki
Kondo Sadao
Yamada Kouichi
Armstrong Westerman & Hattori, LLP
Sanyo Electric Co,. Ltd.
Thomas Tom
Tran Thien F.
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