Transistor structure with minimized parasitics and method of...

Details Transistor structure with minimized parasitics and method of... Transistor structure with minimized parasitics and method of...

2007-08-07

2007-08-07

Sarkar, Asok Kumar (Department: 2891)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

Having heterojunction

C257SE21375

Reexamination Certificate

active

11481070

ABSTRACT:
A transistor having minimized parasitics is provided including an emitter having a recessed extrinsic emitter portion atop an intrinsic emitter portion; a base including an intrinsic base portion in electrical contact with the intrinsic emitter portion and an extrinsic base portion in electrical contact with the intrinsic base portion and electrically isolated from the recessed extrinsic emitter portion by a set of emitter/base spacers; and a collector in electrical contact with the intrinsic base portion. The transistor may further include extrinsic base having top surfaces entirely silicided to the emitter/base spacer. Additionally, the transistor may include a base window opening within the transistor's active area. Methods of forming the above-described transistor are also provided.

REFERENCES:
patent: 5962880 (1999-10-01), Oda et al.
patent: 6346453 (2002-02-01), Kovacic et al.
patent: 6753234 (2004-06-01), Naem
patent: 2003/0057458 (2003-03-01), Freeman et al.

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