Transistor structure having dual shield layers

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257SE29259

Reexamination Certificate

active

08008719

ABSTRACT:
A semiconductor device is formed having lower gate to drain capacitance. A trench (80) is formed adjacent to a drain (20) of the semiconductor device. Trench (80) has a sidewall surface (100) and a surface (90). A doped region (110) is implanted through the sidewall surface (100) of trench (80). A dielectric layer (150) overlies the sidewall surface (100) of trench (80). A shield layer (170) overlies the dielectric layer (150). The shield layer (170) is between a portion of drain (20) and a portion of the gate and gate interconnect of the semiconductor device thereby reducing gate to drain capacitance. The shield layer (170) overlies a minority portion of the surface (90) of trench (80). A second shield layer (270) further reduces gate to drain capacitance.

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patent: 6861702 (2005-03-01), Kitamura
patent: 6998680 (2006-02-01), Kitamura et al.
patent: 7087958 (2006-08-01), Chuang et al.
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patent: 7847350 (2010-12-01), Davies
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patent: 2010/0090275 (2010-04-01), Davies

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