Transistor structure and method of fabrication

Details Transistor structure and method of fabrication Transistor structure and method of fabrication

2002-07-08

2003-11-25

Prenty, Mark V. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S347000, C438S151000, C438S592000

Reexamination Certificate

active

06653700

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of semiconductor integrated circuits, and more specifically, to the ultra large-scale fabrication of submicron transistors.
2. Discussion of the Related Art
Today literally millions of individual transistors are coupled together to form very large-scale integrated (VLSI) circuits, such as microprocessors, memories, and applications specific integrated circuits (ICs). Presently, the most advanced ICs are made up of approximately three million transistors, such as metal oxide semiconductor (MOS) field effect transistors having gate lengths on the order of 0.5 &mgr;m. In order to continue to increase the complexity and computational power of future integrated circuits, more transistors must be packed into a single IC (i.e., transistor density must increase). Thus, future ultra large-scale integrated (ULSI) circuits will require very short channel transistors with effective gate lengths less than 0.1 &mgr;m. Unfortunately, the structure and method of fabrication of conventional MOS transistors cannot be simply “scaled down” to produce smaller transistors for higher density integration.
The structure of a conventional MOS transistor
100
is shown in FIG.
1
. Transistor
100
comprises a gate electrode
102
, typically polysilicon, formed on a gate dielectric layer
104
which in turn is formed on a silicon substrate
106
. A pair of source/drain extensions or tip regions
110
are formed in the top surface of substrate
106
in alignment with outside edges of gate electrode
102
. Tip regions
110
are typically formed by well-known ion implantation techniques and extend beneath gate electrode
102
. Formed adjacent to opposite sides of gate electrode
102
and over tip regions
110
are a pair of sidewall spacers
108
. A pair of source/drain regions
120
are then formed, by ion implantation, in substrate
106
substantially in alignment with the outside edges of sidewall spacers
108
.
As the gate length of transistor
100
is scaled down in order to fabricate a smaller transistor, the depth at which tip region
110
extends into substrate
106
must also be scaled down (i.e., decreased) in order to improve punchthrough characteristics of the fabricated transistor. Unfortunately, the length of tip region
110
, however, must be larger than 0.07 &mgr;m to insure that the later, heavy dose, deep source/drain implant does not swamp and overwhelm tip region
110
. Thus, in the fabrication of a small scale transistor with conventional methods, as shown in
FIG. 1
, the tip region
110
is both shallow and long. Because tip region
110
is both shallow and long, tip region
110
exhibits substantial parasitic resistance. Parasitic resistance adversely effects (reduces) the transistors drive current.


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