Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-12-31
2003-05-20
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S327000, C257S762000
Reexamination Certificate
active
06566707
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a transistor, a semiconductor memory comprising the same and a method of fabricating the same.
2. Description of the Related Art
Nonvolatile semiconductor memories such as a ferroelectric random access memory, an EPROM (erasable and programmable read only memory), an EEPROM (electrically erasable and programmable read only memory) and the like have been recently considered.
A memory cell (memory transistor) of an EPROM or an EEPROM stores charges in a floating gate electrode for storing data in response to presence/absence of the charges while sensing change of a threshold voltage resulting from presence/absence of charges for reading the data. In particular, the EEPROM includes a flash EEPROM entirely erasing data in a memory cell array or dividing the memory cell array into arbitrary blocks for erasing data in units of the blocks.
Memory cells forming the flash EEPROM are roughly classified into a stacked gate memory cell and a split gate memory cell.
In the stacked gate memory cell, a source region and a drain region are formed on a silicon substrate and a floating gate electrode in an electrically floating state is formed on a channel region held between the source region and the drain region through a silicon oxide film. A control gate electrode is formed on the floating gate electrode through a silicon oxide film.
The floating gate electrode and the control gate electrode are identical in size to each other along the direction of the channel length, and stacked with each other with no misalignment. The control gate electrode is extended in a direction perpendicular to that of the channel length to be common to a plurality of floating gate electrodes, for forming a word line.
The flash EEPROM employing stacked gate memory cells having the aforementioned structure has no function of selecting each memory cell itself. If charges are excessively extracted from the floating gate electrode for erasing data, therefore, such a problem of overerasing is caused that the memory cell regularly enters an ON state (conducting state) and is broken.
In order to prevent overerasing, the erasing procedure must be controlled in a peripheral circuit or an external circuit for the memory device.
The split gate memory cell has been developed in order to solve the problem of overerasing in the stacked gate memory cell. For example, U.S. Pat. No. 5,029,130, WO92/18980 (G11C 13/001 3/00) or the like discloses a flash EEPROM employing split gate memory cells.
FIG. 70
is a sectional view of a conventional split gate memory cell
200
. Referring to
FIG. 70
, a source region
202
and a drain region
203
are formed on a surface of a silicon substrate
201
at a prescribed space. A floating gate electrode
206
is formed on a channel region
204
held between the source region
202
and the drain region
203
through a first insulator film
205
of silicon oxide. A control gate electrode
208
is formed on the floating gate electrode
206
through a second insulator film
207
of silicon oxide.
The source region
202
, the drain region
203
, the channel region
204
, the first insulator film
205
, the floating gate electrode
206
, the second insulator film
207
and the control gate electrode
208
form the split gate memory cell (split gate transistor)
200
.
A part of the control gate electrode
208
is arranged on the channel region
204
through an insulator film
209
of silicon oxide. The part of the control gate electrode
208
located on the channel region
204
forms a selection gate electrode
210
. The selection gate electrode
210
, the source region
202
, the drain region
203
and the channel region
204
form a selection transistor
211
for selecting the memory cell
200
itself.
In other words, the split gate memory cell
200
has such a structure that a transistor formed by the gate electrodes
206
and
208
and the regions
202
,
203
and
204
and the selection transistor
211
are serially connected with each other.
The split gate memory cell
200
having the aforementioned structure has a function of selecting itself with the selection transistor
211
. Even if overerasing takes place, therefore, the selection transistor
211
can control conduction and non-conduction of the memory cell
200
, to cause no problem.
A write operation and an erase operation in the split gate memory cell
200
are now described with reference to FIG.
71
and
FIG. 72
, respectively.
(a) Write Operation
In data writing, the potential of the drain region
203
is set at 0 V, a high voltage exceeding 10 V is applied to the source region
202
, and a voltage of about several V is applied to the control gate electrode
208
, as shown in FIG.
71
. Thus, the selection transistor
211
is turned on so that electrons travel from the drain region
203
to the source region
202
.
At this time, the potential of the floating gate electrode
206
, which is capacitively coupled with the source region
202
through the first insulator film
205
and with the control gate electrode
208
through the second insulator film
207
, increases to about 10 V, i.e., a value close to the potential of the source region
202
. Therefore, the electrons travelling through the channel region
204
are attracted by the floating gate electrode
206
and injected into the same beyond a potential barrier of the first insulator film
205
as hot electrons.
When the floating gate electrode
206
thus stores electrons, no channel is formed on the channel region
204
located under the floating gate electrode
206
and no cell current flows even if a positive voltage is applied to the control gate electrode
208
. This state is called a write state, in which the memory cell
200
stores data “0”.
(b) Erase Operation
In data erasing, the potentials of both of the source region
202
and the drain region
203
are set at 0 V and a high voltage exceeding 10 V is applied to the control electrode
208
, as shown in FIG.
72
. In this case, the potential of the floating gate electrode
206
, which is capacitively coupled with the source region
202
through the first insulator film
205
and with the control gate electrode
208
through the second insulator film
207
, reduces to about several V, i.e., a value close to the potential of the source region
202
. Thus, potential difference of about 10 V is caused between the floating gate electrode
206
and the control gate electrode
208
.
Consequently, electrons stored in the floating gate electrode
206
are extracted to the control gate electrode
208
through the second insulator film
207
as a Fowler-Nordheim tunnel current (hereinafter referred to as an F-N tunnel current).
When a positive voltage is applied to the control gate electrode
208
while the electrons are extracted from the floating gate electrode
206
as described above, a channel is formed on the channel region
204
located under the control gate electrode
206
and a cell current flows. This state is called an erase state, in which the memory cell
202
stores data “1”.
At this time, the electrons jump out from a projection
206
a
formed on the floating gate electrode
206
and move toward the control gate electrode
208
. Thus, movement of the electrons is so facilitated that the electrons can be efficiently extracted from the floating gate electrode
206
.
A method of fabricating such a split gate memory cell is disclosed in U.S. Pat. No. 5,045,488, for example. A thin oxide film is formed on the semiconductor substrate
201
and a polysilicon film for forming the floating gate electrode
206
is deposited on the thin oxide film. Thereafter a silicon nitride film is stacked on the polysilicon film and an opening is formed in a portion of the silicon nitride film for forming the floating gate electrode
206
.
Further, the polysilicon film exposed on the opening of the silicon nitride film is oxidized in an oxidizing atmosphere, for forming an oxide film of polysilicon in the opening. Further, the remaining silicon nitrid
Arimoto Mamoru
Kaida Takayuki
Sudo Shoji
Armstrong Westerman & Hattori, LLP
Sanyo Electric Co,. Ltd.
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