Transistor output circuit

Details Transistor output circuit Transistor output circuit

2001-01-22

2002-06-04

Nelms, David (Department: 2818)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Bipolar transistor

C326S018000, C326S033000, C326S078000, C326S089000, C326S124000, C326S128000

Reexamination Certificate

active

06400184

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a transistor output circuit, and in particular, the present invention relates to a transistor output circuit featuring a reduced power consumption and a high speed operation.
2. Description of the Related Art
Recently, a digital communication technology is widely used in a portable communication equipment and so on, and in addition, a trend for an increased communication capacity and higher speed of communication is in progress. In these portable and high speed digital communication technologies, it becomes more popular that the equipment is provided in a more compact size, light-weighted, and a battery operated form.
As one of IC circuits capable of realizing a high speed digital communication, there is an ECL (Emitter-Coupled-Logic) circuit comprised of bipolar transistors.
In the bipolar IC (Integrated Circuit) circuit comprising bipolar transistors, an analog signal after being subjected to a signal processing is converted in an AID (Analog to Digital) converter to a digital signal and is derived from its output terminal, and this output signal is supplied through the above-mentioned ECL circuit to a CMOS (Complementary Metal Oxide Semiconductor) digital circuit for a digital signal processing.
As shown in
FIG. 3
, in the conventional ECL circuit for use in a high speed signal processing, pulse signals of opposite phase are supplied to respective bases of a bipolar transistors Q
1
and Q
2
which have their emitters connected at a common connection point, and this common connection point is further connected to a reference potential VEE (−5.2 V, for example) via a constant current supply I
0
. On the other hand, a collector of the transistor Q
1
is connected to a reference potential of 0V, for example; and a collector of the transistor Q
2
is connected via a load resistance R
1
to the reference potential of 0V.
Further, it is arranged in the circuit of
FIG. 3
such that a base of an output transistor Q
3
is connected with a common connection point between the collector of the transistor Q
2
and the load resistance R
1
, a collector of the transistor Q
3
is connected to the reference potential of 0V, and an emitter of the transistor Q
3
is set normally open, and then an output signal is taken out from an output terminal OUT.
Further, the emitter of the transistor Q
3
is connected to the reference potential VEE (−5.2V) via a resistance R
2
for setting its current from the output terminal OUT. In an output through-rate at a rising time of this ECL circuit is determined by a faculty of its transistor, and a falling time is determined by a value of the resistance R
2
connected to the emitter of the transistor Q
3
, namely the output terminal OUT. In order to speed up its falling time, the resistance value of the resistance R
2
has to be small, but this causes an increased dissipation of current.
Now, with reference to
FIG. 4
, an example of a so-called active pull down circuit or a CCPP (Complementary Coupled Push Pull) circuit will be described.
In differentially connected NPN type transistors Q
11
and Q
12
, a pair of opposite phase signal s are supplied to bases of these transistors Q
11
and Q
12
, and respective emitter thereof are connected together at a common connection point connected to a reference potential GND of 0V via a constant current supply I
10
. Further, a collector of the NPN transistor Q
11
is connected to a reference power supply Vcc via a load resistance R
11
, and a collector of the NPN transistor Q
12
is also connected to the reference power supply Vcc via a load resistance R
12
.
A common connection point between the collector of the NPN transistor Q
11
and the load resistance R
11
is connected via an inverting amplifier A
1
to a base of an emitter follower NPN transistor Q
14
which constitutes a voltage level shift circuit in the next stage. A collector of the transistor Q
14
is connected to the reference power supply Vcc, and its emitter is connected to the reference potential GND of 0V via a constant current source
112
.
Further, a common connection point between the collector of the NPN transistor Q
12
and the load resistance R
12
is connected to a base of an emitter follower PNP transistor Q
13
which constitutes a voltage level shift circuit in the next stage. A collector of the transistor Q
13
is connected to the reference potential GND of 0V, and an emitter thereof is connected to the reference power supply Vcc of 5V via a constant current supply I
11
.
An output stage of the circuit in
FIG. 4
is comprised of a complementary PNP transistor and NPN transistor, wherein the emitter of the PNP transistor Q
13
is connected to a base of an NPN transistor Q
15
, and a collector of this NPN transistor Q
15
is connected to the reference potential GND of 0V.
The emitter of the transistor Q
14
is connected to a base of the PNP transistor Q
16
, and an emitter of the PNP transistor Q
16
is connected to an emitter of the NPN transistor Q
15
. A collector of the PNP transistor Q
16
is connected to the reference potential GND of 0V.
Respective emitters of these PNP transistor Q
16
and NPN transistor Q
15
are connected together at a common connection point which is connected to an output terminal OUT, and an output signal is derived from the output terminal OUT.
Differential signals having an opposite phase to each other are supplied to respective bases of the NPN transistors Q
11
and Q
12
, which constitute a differential amplifier, in which after respective signals supplied to these bases are inverted (180° phase shift), they are derived from respective collectors thereof. A gain of this differential amplifier is determined by one half of its emitter resistance and a ratio of the load resistances R
11
to R
12
.
Signals that are amplified in the differential amplifier up to a predetermined amplitude (pulse waveforms in most cases) are supplied to the bases of the NPN transistor Q
14
and the PNP transistor Q
13
, respectively, which constitute an emitter follower circuit in the next stage, and in which Vf voltage (forward voltage across the base and emitter of transistor; approximately 0.7V) is shifted. More particularly, its signal output to the collector of the NPN transistor Q
11
is inverted in the inverting amplifier, then caused to drop by Vf (V) in the NPN transistor Q
14
, and is supplied to the base of the PNP type output transistor Q
16
.
On the other hand, the signal output to the collector of the NPN transistor Q
12
is caused to rise by Vf (V) in the PNP transistor Q
13
, then is supplied to the base of the NPN type output transistor Q
15
.
Now, assuming that the base of the NPN transistor Q
11
is at “H” level, and the base of the NPN transistor Q
12
is at “L” level, then after inversion of these signals therein, there are derived a signal of “L” level at the collector of the transistor Q
11
, and a signal of “H” level at the collector of the transistor Q
12
.
Thus, the base of the PNP transistor Q
13
becomes “H” (=Vcc) level, and also the emitter thereof becomes “H” (=Vcc) level, as a result, because the base of the NPN type output transistor Q
15
also becomes “H” (=Vcc−Vf) level, it turns ON so as to flow a current from the reference power supply Vcc of 5V toward an output side across the collector and the emitter of the transistor Q
15
. Therefore, the output terminal OUT becomes “H” (=Vcc−Vf) level.
On the other hand, the base of the NPN transistor Q
14
in the next stage is supplied with a signal of “H” (Vcc) level as inverted in the inverting amplifier A
1
. This inverted (pulse) signal of “H” level when transferred to the next stage causes the emitter of the next stage NPN transistor Q
14
to become “H” (Vcc−Vf) level. As a result, because the base of the output PNP transistor Q
16
also becomes “H” (Vcc−Vf) level, the transistor Q
16
turns OFF, and the emitter terminal thereof becomes open. Thereby, the output terminal OUT becomes an “H” level pot

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