Transistor, method for producing an integrated circuit and a...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S384000, C257S412000, C257S411000, C257S410000

Reexamination Certificate

active

10479300

ABSTRACT:
The invention relates to a method for the selective silicidation of contact areas that allow the production of highly integrated circuits, preferably in a SMOS or BiCMOS process. To this end, a metal oxide layer (14) that contains for example praseodymium oxide is deposited onto a prepared wafer (12). A silicon layer (16) and on top of said silicon layer a cover layer (18) is deposited onto the metal oxide layer (14), said cover layer being laterally structured. In a subsequent tempering step in an oxygen-free, reducing gas atmosphere the silicon layer (16) and the metal oxide layer (14) are converted to a metal silicide layer in lateral sections (20, 22) in which the cover layer (18) was previously removed.

REFERENCES:
patent: 4803539 (1989-02-01), Psaras et al.
patent: 4916508 (1990-04-01), Tsukamoto et al.
patent: 5221853 (1993-06-01), Joshi et al.
patent: 6100173 (2000-08-01), Gardner et al.
patent: 6191059 (2001-02-01), Varanasi
patent: 6458678 (2002-10-01), Spikes et al.
patent: 6548877 (2003-04-01), Yang et al.
patent: 7060600 (2006-06-01), Mussig
patent: 2005/0212030 (2005-09-01), Mussig
patent: 100 39 327 (2002-02-01), None
patent: 0 048 849 (1981-09-01), None
patent: 0 171 003 (1985-07-01), None
patent: 0 407 202 (1990-07-01), None
patent: 1 094 514 (2001-04-01), None
Design and Implementation of a VLSI Cordic Processor, by Yze-Yun Sung, Tai-Ming Parng, 1986 IEEE International Symposium on Circuits and Systems (Cat. No. 86CH2255-8) New York, NY, USA, pp. 934-935 vol. 3, Conference: San Jose, CA, USA, May 5-7, 1996.
Generalized CORDIC for Digital Signal Processing, by Lee & Morf, Ch. 1746-7/82/0000-1748 00.75 1982 IEEE, pp. 1748-1751.
Redundant CORDIC Methods with a Constant Scale Factor for Sine and Cosine Computation, by Naofumi Takagi, Tohru Asada, and Shuzo Yajima, IEEE Transactions on Computers, vol. 40, No. 9, Sep. 1991, pp. 989-995.
Double Step Branching CORDIC: A New Algorithm for Fast Sine and Cosine Generation, by Dhananjay S. Phatak, IEEE Transactions on Computers, vol. 47, No. 5, May 1998, pp. 587-602.
Hybrid CORDIC Algorithms, by Shaoyun Wang, Vincenzo Piuri, Earl E. Swartzlander, IEEE Transactions on Computers, vol. 46, No. 11, Nov. 1997, pp. 1202-1207.
Redundant and On-Line CORDIC: Application to Matrix Triangularization and SVD, Milos D. Ercegovac, and Tomas Lang, IEEE Transactions on Computers, vol. 39, No. 6, Jun. 1990, pp. 725-740.
XP-001022227, A unified algorithm for elementary functions, by J.S. Walther, Hewlett Packard Co., Spring Joint Computer Conference, 1971, pp. 379-385.
Discrete Basis and Computation of Elementary Functions, by Jean-Michel Muller, IEEE Transactions on Computers, vol. C-34, No. 9, Sep. 1985, (pp. 857-862).
A VLSI array architecture for realization of DFT, DHT, DCT and DST, by K. Maharatna, A.S. Dhar, Swapna Banerjee, Signal Processing 81 (2001) pp. 1813-1822. (www.elsevier.com/locate/sigpro), , 2001 Elsevier Science B.V.
A VLSI array architecture for Hough transform, by K. Maharatna, Swapna Banerjee, 2001 Pattern Recognition Society, (www.elsevier.com/locate/patcog), published by Elsevier Science Ltd., (pp. 1503-1512).
Multiplierless Array Architecture for Computing Discrete Cosine Transorm, by Manik Chandra Mandal, Anindya Sundar Dhar and Swapna Banerjeet, Computers Elect. Engng vol. 21, No. 1, pp. 13-19, 1995 Copyright 1994, Elsevier Science Ltd.
A Pipelined Computer Architecture for Unified Elementary Function Evaluation, by Michael Andrews and Daniel A. Eggerding, Comput. & Elect. Engng vol. 5, pp. 189-202, Pergamon Press Ltd., 1978.
Complex Arithmetic Through CORDIC, by S. Hitotumatu, Kodai Math. Sem. Rept. 26 (1975), pp. 176-186, received Jun. 4, 1973.
The CORDIC Trigonometric Computing Technique, by Jack E. Volder, IRE Transactions on Electronic Computers, Sep. 1959, pp. 330-334.
VLSI Implementation of Rotations in Pseudo-Euclidean Spaces, by Jean-Marc Delosme, Information Systems Laboratory, Stanford Univ., CA, pp. 927-930, CH1841-6/83/0000-0927, 1983 IEEE .
Algorithms and Accuracy in the HP-35, A lot goes on in that little machine when it's computing a transcendental function, by David S. Cochran, pp. 10-11, Hewlett-Packard Journal (Jun. 1972) vol. 23, No. 10, pp. 10-11.
Very Fast Fourier Transform Algorithms Hardware for Implementation, by Alvin M. Despain, IEEE Transactions on Computers, vol. C-28, No. 5, May 1979, pp. 333-341.
High-k Gate Dielectrics with Ultra-low leakage current based on praseodymium oxide; H.J. Osten, et al; Im Technologiepark; IEEE 2000.
Salicides and alternative technologies for future ICs: Part 1; Jorge A. Kittl, et al; Texas Instruments Inc.; Dallas, TX. Jun. 1999; Solid State Technology; pp. 81-92.
Salicides and alternative technologies for future ICs: Part 1; Jorge A. Kittl, et al; Texas Instruments Inc.; Dallas, TX. Aug. 1999; Solid State Technology; pp. 55-62.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Transistor, method for producing an integrated circuit and a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Transistor, method for producing an integrated circuit and a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Transistor, method for producing an integrated circuit and a... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3760388

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.