Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2001-11-30
2002-07-23
Thompson, Craig (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S272000, C257S330000, C257S334000
Reexamination Certificate
active
06423619
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related to semiconductor devices and, more specifically, to a transistor metal gate structure that minimizes non-planarity effects.
BACKGROUND
As used herein, the term “high-k material” or “high dielectric constant material” refers to any material with a dielectric constant that is greater than silicon dioxide. The dielectric constant of silicon dioxide is approximately 3.9.
As the industry moves to high dielectric constant materials due to electrical problems of using a thin silicon dioxide layer, using polysilicon as a gate electrode can result in the depletion of carriers in the polysilicon gate. To alleviate the polysilicon depletion problem, metal gate structures can be used.
One method used to form transistor metal gate structures includes depositing metal layers within a gate trench, meaning a trench where a gate will subsequently be formed, and along the top surface of insulating materials surrounding the gate trench. An etch back or polishing process is used to remove the portions of the metal layers lying outside the gate trench.
When removing the metal layers using chemical mechanical polishing (CMP), dishing can occur across the semiconductor wafer and when using etch back the insulating materials around the gate trench can erode. This results in non-functional devices, which decreases yield. Therefore, there is a need for a semiconductor process that minimizes non-planarity effects when removing the metal layers outside the gate trench.
REFERENCES:
patent: 5364817 (1994-11-01), Lur et al.
patent: 5674781 (1997-10-01), Huang et al.
patent: 6087231 (2000-07-01), Xiang et al.
patent: 6140224 (2000-10-01), Lin
patent: 6150260 (2000-11-01), Roy
patent: 6171910 (2001-01-01), Hobbs et al.
patent: 6200886 (2001-03-01), Yu et al.
patent: 6221721 (2001-04-01), Takahashi
patent: 6285073 (2001-09-01), Cooper et al.
Adetutu Olubunmi O.
Grant John M.
Musgrove Yolanda S.
King Robert L.
Motorola Inc.
Thompson Craig
Vo Kim-Marie
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