Transistor, memory cell array and method of manufacturing a...

Details Transistor, memory cell array and method of manufacturing a... Transistor, memory cell array and method of manufacturing a...

2006-09-08

2009-11-03

Wilson, Allan R. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257SE27091

Reexamination Certificate

active

07612406

ABSTRACT:
A transistor includes a first and second source/drain regions, a channel connecting the first and second source/drain regions, and a gate electrode to control an electrical current flowing in the channel. The gate electrode is disposed in a gate groove, the gate groove being defined in a top surface of a semiconductor substrate. The first and second source/drain regions extend at least to a depth d1, the depth d1being measured from the top surface of the substrate. A top surface of the gate electrode is disposed beneath the top surface of the semiconductor substrate. A top surface of the gate electrode is disposed at a depth d2which is less than the depth d1, the depth d2being measured from the substrate surface.

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