Transistor, memory cell array and method for forming and...

Static information storage and retrieval – Associative memories – Ferroelectric cell

Reexamination Certificate

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C365S104000, C257S296000

Reexamination Certificate

active

07359226

ABSTRACT:
A substrate forming an array of vertical transistor cells for selecting one of a plurality of memory cells and wherein each memory cell couples a transistor to a bit line via a memory element and is addressable by selecting two word lines and a bit line is disclosed. For minimizing the area of a cell and reducing complexity in production, one word line trench takes one word line, wherein in a first embodiment a first word line in a first word line trench forms a plurality of gate electrodes on one sidewall of active areas of a first and a second, adjacent row of transistor cells in word line direction, and wherein a second word line in an adjacent word line trench forms a plurality of gate electrodes on the opposite sidewall of active areas of the second and of a third row of transistor cells in wordline direction.

REFERENCES:
patent: 6902942 (2005-06-01), Wu et al.
patent: 2005/0254279 (2005-11-01), Schwerin
patent: 2006/0113587 (2006-06-01), Thies et al.
patent: 102004021051 (2005-11-01), None
patent: 102005029493 (2006-02-01), None
patent: 102005046426 (2006-04-01), None
patent: 1097457 (2003-04-01), None

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