Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2006-05-30
2006-05-30
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S051000, C365S063000
Reexamination Certificate
active
07054219
ABSTRACT:
A multi-headed word line driver circuit incorporates bent-gate transistors to reduce the pitch otherwise achievable for interfacing to tightly-pitched array lines. In certain exemplary embodiments, a three-dimensional memory array includes multiple memory blocks and array lines traversing horizontally across at least one memory block. Vertical active area stripes are disposed beneath a first memory block, and a respective plurality of bent-gate electrodes intersects each respective active area stripe to define individual source/drain regions. Every other source/drain region is coupled to a bias node for the active area stripe, and remaining source/drain regions are respectively coupled to a respective array line associated with the first memory block, thereby forming a respective first driver transistor for the respective array line.
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Bandyopadhyay Abhijit
Kumar Tanmay
Petti Christopher J.
Scheuerlein Roy E.
Dinh Son T.
Matrix Semiconductor Inc.
Zagorin O'Brien Graham LLP
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