Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-07-19
2003-07-01
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S040000, C257S310000, C257S411000, C257S412000, C257S513000
Reexamination Certificate
active
06586791
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to high dielectric insulating layers for use in transistors, and in particular, organic layers.
2. Description of the Related Art
A typical field effect transistor (“FET”) starts with a gate electrode applied to a substrate. An insulating layer then is applied on top of the gate electrode, sometimes overlapping onto the substrate. Source and drain electrodes then are applied on top of the insulating layer, spaced slightly apart with the gap between them positioned above the gate electrode. Finally, a layer of semiconductor is applied to fill the gap between the source and drain electrodes, often overlapping onto the top of the source and drain electrodes. The presence or absence of an appropriate voltage at the gate electrode then will drive the semiconductor into its conductive or non-conductive states, either electrically connecting or disconnecting the source and drain electrodes.
In an FET made with a semiconductor, some carriers (holes or electrons, depending on whether the semiconductor is a p-type or n-type semiconductor) in the semiconductor will be induced at the interface between the gate insulator and the semiconductor when a voltage is applied to the gate electrode. The carriers induced by this low gate bias voltage will first fill the trap levels, but may not be enough to completely fill those levels. Therefore, even at high drain voltages but at low gate bias voltages, one still cannot collect pronounced free carriers that can move freely from the source side to the drain side.
When the gate bias voltage is high enough (greater than a threshold voltage, V
T
), more carriers will be induced. They can not only fill all the trap levels, but also have excessive carriers left, which can then be pushed to the conduction band of the semiconductor, where they are free to move. The potential difference between the drain and the source electrodes will then drive those free carriers to move from the source electrode to the drain electrode.
The current-voltage characteristics for a FET device are qualitatively modeled by the following equations:
Linear Region: |
V
GS
−V
T
51
>|V
DS
| (1)
I
D
=
Wc
i
L
μ
(
V
GS
-
V
T
-
V
DS
/
2
)
V
DS
Saturation Region: |
V
GS
−V
T
|≦|V
DS
| (2)
I
D
=
Wc
i
2
L
μ
(
V
GS
-
V
T
)
2
in which:
c
i
is the capacitance per unit area of the gate electrode=C/A;
&mgr; is the field-effect mobility of the semiconductor;
I
D
is the current through the drain electrode;
L is the channel length between the source electrode and the drain electrode;
V
DS
is the voltage between the drain and source electrodes;
V
GS
is the voltage between the gate and source electrodes;
V
T
is the threshold voltage described above; and
W is the width of the channel, i.e., the width of the source and drain electrode pads.
The geometric parameters of the FET, such as the channel length and width, are defined by the mask pattern used to make the FET, and will certainly affect the device performance. As will be apparent from the equations, it is desirable to keep them as small as possible to achieve high current and high resolution (or high density). However, the size of the patterns usually is dictated mostly by the manufacturing process used to generate the patterns, with more sophisticated (and expensive) equipment needed to generate very small pattern sizes.
The equations highlight two other parameters which can potentially be adjusted as needed to achieve high currents at low operating voltages (V
DS
and V
GS
), namely, generating a high capacitance and high field effect mobility to get a high current, I
D
. High mobility usually is a function of the semiconductor used. High capacitance is dependent on the thickness of the insulating layer (the thinner, the better) and the dielectric constant of the insulating layer (the higher, the better). Therefore, one way to maximize the current I
D
at low voltages is to provide a thin insulating layer formed of a material with a high dielectric. At the same time, the insulating layer should be free of pinholes and have a high breakdown voltage to continue functioning as an insulator even when it is very thin. It also needs to be compatible with the subsequent processes needed to complete device and circuit fabrications, which means it should have a good chemical resistance.
Conventionally, all of the layers involved are inorganic materials. Most commonly, the substrate is crystalline silicon, the electrodes are metal, the insulating layer is silicon dioxide and the semiconductor is crystalline, polycrystalline or amorphous silicon. Well known alternatives use III-V semiconductors, such as gallium arsenide. All are characterized by high processing temperatures well in excess of 200° C.
Recently, there has been considerable interest in developing an organic field effect transistor (“OFET”). OFETs have the following potential advantages when compared with inorganic FETs:
(1) They can be produced using low cost processing methods, e.g., spin coating, web coating, inkjet printing and vacuum evaporation to form the active layers. It is even possible to do this on a moving web, rather than in batches on crystalline or glass wafers.
(2) They provide excellent compatibility with many different kinds of substrates (e.g., flexible plastic substrates, glass, metal foils, etc.), and can be made in very large sizes, i.e., they are not limited to the size to which crystals can be grown.
(3) The molecular structures and orientation for both the organic semiconductors and the substrates can be tailored with desired properties.
Due to these potential benefits, dramatic progress has been made in the development of OFETs, attracting increasing attention in both academic and industrial laboratories around the world. Gundlach, D. J., Kuo, C-C., Nelson, S. F., and Jackson, T. N., “Organic thin film transistors with field effect mobility >2 cm
2
/V-s,” 57
th Annual Device Research Conference Digest
, pp. 164-165, June, 1999, reported pentacene-based OFETs with a field effect mobility as large as 2.1 cm
2
/V-s, which is higher than amorphous silicon. Dimitrakopoulos, C. D., Purushothaman, S., Kymissis, J., Callegari, A., Shaw, J. M., “Low-voltage organic transistors on plastic comprising high-dielectric constant gate insulators,”
Science
, Feb. 5, 1999, Vol. 283, pp. 822-824, reported OFETs with a low operating voltage (<5 V) and a high mobility (~0.4 cm
2
/V-s) by employing a high dielectric constant insulating film using barium zirconate titanate (BZT) and barium strontium titanate (BST) on a polycarbonate substrate.
OFETs are considered strong candidates for use in integrated circuits (ICs) in applications such as radio frequency identification (RFID) tags, digital displays, digital logic circuits and many other applications.
Unfortunately, one of the disadvantages to using OFETs is that the materials involved cannot withstand the high processing temperatures used with conventional inorganic materials. For example, the 200+° C. temperatures needed to process conventional inorganic materials would at the very least cause a polymeric substrate to deform, and might cause further breakdown of the polymer or even ignition at high enough temperatures. Deformation is highly undesirable, since each layer of the structure has to be carefully registered with the layers below it, which becomes difficult to impossible when the layers below it are deformed due to processing temperatures.
SiO
2
, SiN
x
, AlO
x
, and TaO
x
are the most popular dielectric materials employed in both inorganic and organic semiconductor FETs. However, the conventional methods for depositing these materials, such as chemical vapor deposition (CVD) and plasma enhanced CVD, need high temperatures (>300° C.) which are not compatible with polymeric substrates. Without such high processing temperatures, poor film quality and pinholes are typically unavoidable, resulti
Lee Tzu-Chen
O'Bryan Nelson B.
3M Innovative Properties Company
Dennis II Charles L.
Fenty Jesse A.
Lee Eddie
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