Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
1998-01-15
2001-01-23
Monin, Jr., Donald L. (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S219000, C438S227000, C438S244000, C438S284000, C438S406000, C257S401000, C257S329000
Reexamination Certificate
active
06177299
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to integrated circuit devices, and more specifically to field effect transistors.
BACKGROUND OF THE INVENTION
Increased gate control, reduced body effect, reduced junction capacitance and lower junction leakage current are among the attributes of insulated gate field effect transistors (IGFETs) including metal-oxide-semiconductor field effect transistors (MOSFETs) fabricated in semiconductor-on-insulator (SOI) substrates. These attributes of SOI IGFETs have generated interest in their use in low voltage, low power applications. However, problems unique to the fabrication of devices on SOI substrates complicate the design of circuits thereon and add to the costs of development and production.
Unlike IGFET devices constructed on bulk silicon substrates which have bodies in electrical contact with the substrate and thereby exchange charge carriers with the substrate, SOI IGFETs have floating bodies which store charge carriers on a permanent or near permanent basis. This characteristic of SOI IGFET devices results in their electrical properties exhibiting hysteresis effects, wherein the SOI device behaves electrically as a function of its state during the preceding several hundred milliseconds of operation. In addition, the floating body of the SOI IGFET has been linked to reliability problems, such as increased susceptibility to device latch-up and increased hot carrier degradation as compared to conventional IGFETs built in bulk silicon substrates.
An obstacle to the acceptance of SOI IGFETs is the increased cost of SOI substrate fabrication, which involves additional process steps, for example, high dose oxygen implantation with long duration anneals at high temperature in silicon-implanted-with-oxygen (SIMOX) substrates, or the bonding of two prepared wafers and the polishing down of the top semiconductor layer to the desired thickness, as in bond-and-etchback SOI (BESOI).
Accordingly, it is an object of the invention to provide a field effect transistor having a substantially isolated body which nevertheless remains joined to a substrate for exchange of charge carriers therewith.
Another object of the invention is to provide a field effect transistor having a substantially isolated body to facilitate rapid switching speed, while maintaining body contact to substrate to avoid the deleterious results of the floating body described above.
Still another object of the invention is to provide a field effect transistor having a very short effective channel length.
Another object of the invention is to provide a field effect transistor having reduced junction capacitance.
A further object of the invention is to provide a method of fabricating a field effect transistor which has large channel width but occupies a small area of the semiconductor substrate.
Another object of the invention is to provide a field effect transistor having a body which has sublithographic thickness for providing enhanced device current.
Still another object of the invention is to provide a field effect transistor (FET) in which the gate conductor is wrapped around the body of the FET and the FET is electrically isolated from other circuit elements on the substrate by large isolation regions.
SUMMARY OF THE INVENTION
These and other objects are provided by the transistor having a substantially isolated body and method of fabricating the same of the present invention.
According to a first aspect of the invention, a field effect transistor (FET) includes a substantially isolated body, i.e., channel region, of semiconductor material joined to a semiconductor substrate through a neck region which permits exchange of charge carriers with the substrate. The body of the transistor is isolated from electrical contact with the substrate at surfaces other than the neck.
According to a preferred aspect of the invention, the body of the FET is formed on a sidewall of an isolation region in the substrate. In another preferred aspect of the invention, the body has a plurality of electrically isolated surfaces which comprise substantially all surface area of the body other than the surface at the neck, and the gate covers all of the electrically isolated surfaces.
In another preferred aspect of the invention, the body is formed in a sidewall spacer region of epitaxial semiconductor material having sublithographic thickness and which contacts a monocrystalline semiconductor substrate. Preferably, the substrate is implanted with dopant ions in a first implanting and a body region and source/drain regions are formed in the sidewall spacer region by a second implantation of dopant ions to form doped active device regions in registration with doped substrate regions.
In still another aspect of the invention, a method for forming a field effect transistor (FET) is provided which includes forming an isolation region in a semiconductor substrate, depositing a conformal material layer over the substrate, and anisotropically etching the conformal material and underlying semiconductor material such that semiconductor material remains on a sidewall of the isolation region as an active device region of the FET. Channel and source/drain regions are then formed by doping respective portions of the active device region to form respective doped regions of opposite dopant type.
In a preferred aspect of the invention, a method for forming a field effect transistor (FET) is provided which includes providing a semiconductor substrate having an upper layer of a first dopant concentration, a lower layer of a second dopant concentration, wherein the second dopant concentration is different from the first dopant concentration such that the lower layer forms an etch stop layer. A shallow trench isolation region is formed in the substrate and the upper layer is anisotropically etched until the etch stop layer is exposed such that material from the upper layer remains on a sidewall of the isolation region as a body of the FET. Then, doping concentrations in regions of the body are altered to form source-drain regions of a first dopant type and a channel region of a second dopant type opposite to the first dopant type. A gate is formed which overlays the channel region.
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Hsu Louis Lu-Chen
Mandelman Jack Allan
International Business Machines - Corporation
Monin, Jr. Donald L.
Neff Daryl K.
Rao S. H.
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