Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-08-25
2002-12-17
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S285000, C257S286000, C257S402000, C257S403000, C438S143000, C438S282000, C438S514000, C438S543000
Reexamination Certificate
active
06495891
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a refined transistor, and more particularly to an impurity concentration profile in a channel region of a transistor.
In recent years, as semiconductor devices are refined, a technique for suppressing short channel effect in a MOS (MIS) transistor has become important. A MOS transistor has a threshold voltage determined by the thickness of a gate oxide film, the impurity concentration of a channel region, the material of a gate electrode, etc. The threshold voltage does not essentially depend on the channel length. However, as the channel length is decreased with refinement of the device, the threshold voltage is lowered by two-dimensional effect, such as a decrease in space charge in a surface depletion layer in the channel region and a reduction in potential barrier at an end of a source region. This is called short channel effect. When the channel is shorter than a certain length, the threshold voltage is abruptly reduced, resulting in malfunction of the MOS transistor.
A conventional MOS transistor will be described with reference to
FIGS. 1
to
3
.
FIG. 1
shows a cross section of a MOS transistor.
As shown in
FIG. 1
, a gate electrode
11
is formed on a gate oxide film
12
, which is formed on a semiconductor substrate
10
. Impurity diffusion layers serving as source and drain regions
13
and
14
are formed by ion implantation in the semiconductor substrate
10
on both sides of the gate electrode
11
. The part of the semiconductor substrate
10
between the source and drain regions
13
and
14
serves as a channel region
15
.
FIG. 2
shows an impurity concentration profile of the channel region
15
along the depth direction with respect to the distance from the substrate surface of the conventional MOS transistor taken along the line
2
—
2
′ in FIG.
1
. As shown in
FIG. 2
, generally, the impurity concentration is kept constant with respect to the depth (case
1
) or the concentration is distributed such that the concentration in the surface region is high and gradually lowered with the depth in consideration of the controllability of the threshold voltage (case
2
).
FIG. 3
shows the dependence of a threshold voltage Vth on a channel length L in a MOS transistor having distribution of the impurity concentration in the channel region as described above. The thickness Tox of the gate insulating film
12
is 60 Å and the diffusion depth Xj of the source and drain regions
13
and
14
is 0.12 &mgr;m. The impurity concentration is set such that the threshold voltage Vth is 0.60V in the case where the channel length L is satisfactorily long.
As shown in
FIG. 3
, in the case
1
wherein the impurity concentration in the channel region is kept constant at 4.67×10
17
cm
−3
, the threshold voltage Vth is gradually lowered as the channel length L becomes shorter. When the channel length L is about 0.30 &mgr;m, the threshold voltage Vth is 0.5V. When the channel length L is 0.20 &mgr;m, the threshold voltage Vth is 0.308V and the MOS transistor does not perform the essential functions thereof.
In the case
2
wherein the impurity concentration of the surface region of the semiconductor substrate
10
is distributed such that it is at its peak 1.05×10
18
cm
−3
on the surface of the semiconductor substrate (the impurity concentration is 1.0×10
17
cm
−3
) and gradually lowered with the distance below the surface, the short channel effect is greater than in the case
1
. Thus, the condition is far from desirable from the viewpoint of reliability of the operation of the MOS transistor.
For this reason, in the conventional semiconductor device, the channel length L of a MOS transistor must be strictly controlled, or the thickness Tox of the gate oxide film or the diffusion depth Xj of the source and drain regions
13
and
14
must be reduced, so that the short channel effect can be suppressed. As a result, the manufacturing is burdened and a highly-developed technique is required.
In addition, as described above, the conventional MOS transistor, in which the impurity concentration in the channel region is kept constant or distributed so as to reduce with the depth, has a problem that the short channel effect is significant and hinders refinement of the MOS transistor. Further, the short channel effect adversely influences the reliability of the MOS transistor.
A proposal for reducing the short channel effect of the MOS transistor as described above is disclosed in IEEE TRANSACTIONS ON ELECTRON DEVICES (1989) Vol. 36, p 2605, G. G. Shahidi et al., “Indium Channel Implants for Improved MOSFET Behavior at 100-nm Channel Length Regime”. According to this prior art reference, the impurity concentration is set low in a surface region of a semiconductor substrate in order to suppress reduction of mobility due to impurity scattering, and set high in a deep portion of the semiconductor substrate in order to suppress the short channel effect. According to another prior art reference, ELECTRON DEVICES (1987) Vol. 34, p 19, Sun et al., “Submicrometer-Channel CMOS for Low-Temperature Operation”, the impurity concentration profile is set to a Gaussian distribution in which the concentration is at its peak in an inner portion of the substrate, thereby obtaining high mobility and low junction capacitance.
However, these reports of the prior art merely describe a tendency for the distribution of the impurity concentration to influence the mobility or the short channel effect. Therefore, to realize an actual device free from the above problems, a number of other factors must be further considered and optimized.
BRIEF SUMMARY OF THE INVENTION
A semiconductor device according to an aspect of the present invention comprises: source and drain regions spaced apart from each other in a semiconductor layer; a gate insulating film formed on a surface of the semiconductor layer between the source and drain regions; a gate electrode formed on the gate insulating film, said gate insulating film being interposed between the semiconductor layer and the gate electrode; and a channel region, formed in contact with at least a portion of the gate insulating film, including a region where carriers move between the source and drain regions, an impurity concentration of said channel region being higher at an end portion of a surface depletion layer, formed of a MIS structure comprising the gate electrode, the gate insulating film and the semiconductor layer, than at an interface between the semiconductor layer and the gate insulating film; wherein the impurity concentration varies along a direction in which the gate electrode, the gate insulating film and the channel region are successively provided, and it increases substantially linearly near the end portion of the surface depletion layer.
REFERENCES:
patent: 5753943 (1998-05-01), Okabe et al.
patent: 5874329 (1999-02-01), Neary et al.
patent: 6020608 (2000-02-01), Kamashita
G.G.Shahidi etal. “Electron Velocity OVershoot at room and Liquid Nitrogen Temperatures in Sllicon Inversion layers”, IEEE Electron Device Lett., vol. 9, No. 2, pp94-96, Feb. 1988.*
Richard C. Jaeger, “Microelectronic Circuit Design”, pp 118-119, McGraw Hill.*
J. B. Jacobs et al., “Channel Profile Engineering For MOSFET's With 100 nm Channel Lengths,”IEEE Transactions On Electron Devices, vol. 42, No. 5, May 1995, pp. 870-875.
Shahidi, G.G., et al., “Indium Channel Implants for Improved MOSFET Behavior at the 100nm Channel Length Regime”, IEEE Transactions on Electron Devices (1989), vol. 36, p. 2605.
YuanChen Sun, J. et al., “Submicrometer-Channel CMOS for Low-Temperature Operation”, Electron Devices (1987), vol. 34, p. 19.
Kinoshita Hiroyuki
Shimane Takeshi
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kang Donghee
Loke Steven
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