Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor
Reexamination Certificate
2001-07-06
2004-06-22
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Junction field effect transistor
C438S182000, C438S183000, C257S284000, C257S330000
Reexamination Certificate
active
06753559
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to the field of electronic devices, and more particularly to a transistor having an improved gate structure and method of construction.
BACKGROUND OF THE INVENTION
Electronic equipment such as televisions, telephones, radios, and computers are often constructed using semiconductor components, such as integrated circuits, memory chips, and the like. The semiconductor components are constructed from various microelectronic devices, such as transistors, capacitors, diodes, resistors, and the like. These microelectronic devices, and in particular the transistor, may be formed on a semiconductor substrate.
A transistor generally includes a gate formed on the semiconductor substrate that operates to control the flow of current through the transistor. The dimensions of the gate are carefully controlled to precisely control the flow of current through the transistor and to prevent leakage or shorting in the transistor. One such dimension that is carefully controlled is the width of the gate. Some gate fabrication techniques construct side wall bodies during the gate fabrication process to control the width of the gate and to aid in constructing the source and drain regions of the microelectronic device. The use of side wall bodies will typically increase the complexity, fabrication time, and cost of the transistor and the corresponding semiconductor components.
Some gate fabrication techniques may also utilize an etching process, such as plasma etching or wet chemical etching, to chemically remove material to form and pattern the transistor. The etching processes used in some gate fabrication processes can remove material that would otherwise be beneficial to the construction or operation of the gate. The loss of the beneficial material during these etching processes may reduce the manufacturability or operating ability of the gate, transistor, and the semiconductor component.
SUMMARY OF THE INVENTION
Accordingly, a need has arisen for a transistor having an improved gate structure and method of construction. The present invention provides a transistor having an improved gate structure and method of construction that substantially eliminates or reduces disadvantages and deficiencies associated with prior devices and methods.
In accordance with one embodiment of the present invention, an improved gate structure of a transistor may be fabricated by forming a primary insulation layer adjacent a substrate. The primary insulation layer is comprised of a first material. A disposable gate is then formed outwardly from the primary insulation layer. An isolation dielectric layer is then formed outwardly from the primary insulation layer. The isolation dielectric layer is comprised of a second material, wherein the second material is different than the first material. The disposable gate is removed to expose a portion of the primary insulation layer. The exposed portion of the primary insulation layer is then removed to expose a portion of the substrate. The primary insulation layer is selectively removable relative to the isolation dielectric layer by using an etch that is selective to the first material relative to the second material. A gate insulator is then formed on the exposed portion of the substrate, and a gate is then formed adjacent the gate insulator. In a particular embodiment, the gate has a T-gate configuration.
In accordance with another embodiment of the present invention, a method of fabricating a semiconductor component comprises the steps of: forming a primary insulation layer adjacent a semiconductor substrate; forming a disposable gate adjacent the primary insulation layer; forming a silicon oxynitride layer over the primary insulation layer and the disposable gate, said layer having a depth which is greater than a depth of the disposable gate; removing an upper portion of the silicon oxynitride layer which lies higher than the disposable gate, such that at least a portion of the disposable gate is exposed; removing the disposable gate to expose a portion of the primary insulation layer, the disposable gate being selectively removable relative to the silicon oxynitride layer; removing the exposed portion of the primary insulation layer to expose a portion of the semiconductor substrate, the primary insulation layer being selectively removable relative to the silicon oxynitride layer; forming a gate insulator adjacent the exposed portion of the semiconductor substrate; and forming a gate adjacent the gate insulator.
In accordance with another embodiment of the present invention, a gate structure comprises: a semiconductor substrate having a channel region; a gate insulator adjacent the channel region of the semiconductor substrate; a conductible gate adjacent the gate insulator; a primary insulation layer adjacent the semiconductor substrate, said primary insulation layer having an opening where the gate insulator contacts the semiconductor substrate; and an isolation dielectric layer adjacent the primary insulation layer, said isolation dielectric layer having an opening where the conductible gate is located, and said isolation dielectric layer comprising a silicon oxynitride material.
Important technical advantages of the present invention include providing an improved gate structure in which the isolation dielectric layer is not substantially removed during the disposable gate removal process or the primary insulation layer removal process. Thus, an adequate distance between the gate and the conducting source and drain regions of the transistor is maintained. Accordingly, the transistor will have an increased resistance to charge leakage and shorting between the gate and the source or drain regions. Additionally, the gate to drain capacitance and the gate to source capacitance are not significantly increased during the removal of the disposable gate and the oxide layer underlying said gate.
Another technical advantage of the present invention includes providing an improved gate structure that does not require a sidewall body during manufacturing. The sidewall bodies associated with some gate structures can form ear-like structures that extend above the surface of the isolation dielectric layer due to the removal of the isolation dielectric layer after the sidewall body is formed. These ear-like structures may be fragile and lead to problems in later fabrication processes, such as the formation of a T-gate structure. In particular, a T-gate configuration may be prone to damage due to the ear-like structure associated with the sidewall bodies.
A further technical advantage of the present invention is that the process of fabricating the improved gate structure includes fewer fabrication operations. Accordingly, the improved gate structure may be less expensive to fabricate than some gate structures.
Other technical advantages will be readily apparent to one skilled in the art from the following figures, description, and claims.
REFERENCES:
patent: 4717681 (1988-01-01), Curran
patent: 4901133 (1990-02-01), Curran et al.
patent: 5236862 (1993-08-01), Pfiester et al.
patent: 5369052 (1994-11-01), Kenkare et al.
patent: 5688704 (1997-11-01), Liu
patent: 5789315 (1998-08-01), Besser et al.
patent: 5824587 (1998-10-01), Krivokapic
patent: 5856225 (1999-01-01), Lee et al.
patent: 5937302 (1999-08-01), Gardner et al.
patent: 5960270 (1999-09-01), Misra et al.
patent: 5976924 (1999-11-01), Gardner et al.
patent: 5994179 (1999-11-01), Masuoka
patent: 5998285 (1999-12-01), Chou
patent: 6051486 (2000-04-01), Gardner
patent: 6063675 (2000-05-01), Rodder
patent: 6063677 (2000-05-01), Rodder et al.
patent: 6121133 (2000-09-01), Iyer et al.
Ali Iqbal
Chatterjee Amitava
Hames Greg A.
Hanratty Maureen
He Qizhi
Brady III Wade James
Le Thao X.
Pham Long
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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