Transistor having dielectric stressor elements for applying...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S414000, C438S149000, C438S412000

Reexamination Certificate

active

11163686

ABSTRACT:
A chip is provided which includes an active semiconductor region and a field effect transistor (“FET”) having a channel region, a source region and a drain region all disposed within the active semiconductor region. The FET has a longitudinal direction in a direction of a length of the channel region, and a transverse direction in a direction of a width of the channel region. A first dielectric stressor element having a horizontally extending upper surface extends below a portion of the active semiconductor region, such as a northwest portion of the active semiconductor region. A second dielectric stressor element having a horizontally extending upper surface extends below a second portion of the active semiconductor region, such as a southeast portion of the active semiconductor region. Each of the first and second dielectric stressor elements shares an edge with the active semiconductor region, the edges extending in directions away from the upper surface.

REFERENCES:
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patent: 6884667 (2005-04-01), Doris et al.
patent: 2004/0113174 (2004-06-01), Chidambarrao et al.
patent: 2004/0217448 (2004-11-01), Kumagai et al.
patent: 2005/0067294 (2005-03-01), Choe et al.
patent: 2005/0263825 (2005-12-01), Frohberg et al.
patent: 2006/0202280 (2006-09-01), Shima et al.
W. Theiss, “Optical Properties of Porous Silicon”, I. Physikalisches Institut, Aachen University of Technology (RWTH), D-52056 Aachen, Germany, Surface Science Reports, vol. 29, 1997, pp. 91-192.

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