Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Patent
1998-12-15
2000-04-11
Thomas, Tom
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
438302, 438303, 438308, 438798, 438800, 257309, 257401, 257388, H01L 213205, H01L 21336, H01L 21477
Patent
active
060487844
ABSTRACT:
A method of fabricating a transistor having an improved salicided gate is provided. The method may include forming a gate (14) that is separated from a substrate (12) by a gate insulator (16). A spacer (22) may be formed proximate the gate (14) such that the spacer (22) exposes a top region (28) and a side region (30) of the gate (14). The top region (28) and the side region (30) of the gate (14) may be irradiated at an angle (38) to form a post amorphous region (32) within the gate (14). A reactive layer (42) may be formed adjacent the post amorphous region (32). A salicidation region (44) may be then formed between the post amorphous region (32) and the reactive layer (42). The reactive layer (42) may be removed to expose the salicidation region (44).
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Hong Qi-Zhong
Kittl Jorge A.
Brady Wade James
Donaldson Richard L.
Garner Jacqueline J.
Snow Bernard E.
Texas Instruments Incorporated
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