Transistor having an etchant-scalable channel length and method

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257330, 257635, 257752, 257758, 257776, 438585, H01L 2976

Patent

active

060722134

ABSTRACT:
An integrated circuit fabrication process is provided for forming a transistor having an ultra short channel length. First and second masks are formed upon a conductive gate layer, wherein the second mask has a second lateral dimension less than a first lateral dimension of the first mask. The second mask is used to pattern a gate conductor from the conductive gate layer such that the gate conductor has an ultra narrow lateral dimension. Lightly doped drain impurity areas are formed self-aligned to sidewall surfaces of the gate conductor. Spacers are formed laterally adjacent the sidewall surfaces of the gate conductor, and source and drain impurity areas are formed self-aligned to sidewall surfaces of the spacers.

REFERENCES:
patent: 5708303 (1998-01-01), Jeng
patent: 5744866 (1998-04-01), Horiba
patent: 5793082 (1998-08-01), Bryant
patent: 5910684 (1999-06-01), Sandhu
patent: 5929483 (1999-07-01), Kim et al.
patent: 5949144 (1999-09-01), Delgado et al.
patent: 5952702 (1999-09-01), Gardner et al.

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