Transistor having a deposited dual-layer spacer structure

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S900000

Reexamination Certificate

active

06720631

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor processing and more particularly to a transistor having spacers formed from a deposited dual-layer film.
BACKGROUND OF THE INVENTION
Metal-oxide-semiconductor (MOS) transistors are the primary building blocks for modem integrated circuits. Today, highly complex integrated circuits such as, for example, microprocessors and memory chips, contain millions of transistors on a single silicon substrate no bigger than a thumbnail. A transistor may be thought of as an electronic switch having three nodes. According to a voltage applied to a first node of the transistor, called the gate, the flow of electric current between the other two nodes, called the source and drain, is modulated. For example, to turn one type of n-channel (NMOS) transistor “on,” a positive voltage is applied to the gate, allowing electric current to flow between the source and drain. To turn this transistor “off,” zero volts is applied to the gate which cuts off the flow of electric current between the source and drain.
As the demand for cheaper, faster, lower power consuming electronic products increases, the speed of the integrated circuits utilized by these devices must be similarly increased. One way to increase the speed of an integrated circuit is to reduce the “switching speed” of the transistors contained within the integrated circuit. The switching speed of a transistor is the amount of time associated with turning the transistor from an “off” state to an “on” state, or from an “on” state to an “off” state. In addition to improving the switching speed of a transistor, the reliability of a transistor must similarly be improved to improve the reliability of the overall integrated circuit.
There are many factors which affect the speed and reliability of a transistor.
FIG. 1A
shows an edge of a transistor comprising a source/drain tip region
11
formed in a silicon substrate
10
. Gate oxide
12
separates polysilicon gate electrode
13
from semiconductor substrate
10
. Typically, after tip region
11
is formed in silicon substrate
10
by implanting dopants into the substrate, a reoxidation step is carried out. During reoxidation, the substrate of
FIG. 1A
is exposed to an oxidizing ambient at elevated temperatures. During reoxidation, any bare silicon exposed to the oxidizing ambient will grow a silicon dioxide (oxide) layer.
FIG. 1B
shows the cross-section of
FIG. 1A
after the substrate has been reoxidized. The exposed silicon of polysilicon gate electrode
13
and silicon substrate
10
combines with oxygen in the oxidizing ambient to grow reox layer
14
. Reox layer
14
serves many useful purposes. For example, the reox layer protects the underlying substrate from contamination by subsequently deposited materials such as, for example, photolithographic resist and interlayer dielectrics. The thermal process step used to grow reox layer
14
also helps to repair damage caused by implanting tip region
11
.
In addition, reox layer
14
will encroach underneath polysilicon gate electrode
13
within region
15
to round-off and separate the lower corner of the gate electrode from the underlying tip region
11
. By separating the gate electrode from the tip region in this manner, the gate-to-source and gate-to-drain capacitance, known as Miller capacitance, is reduced. Reduction in Miller capacitance is known to improve the switching speed of a transistor. Also, the portion of reox layer
14
which grows in region
15
serves to protect the delicate edges of gate oxide
12
from damage and serves to reduce hot electron damage to gate oxide
12
, a major reliability concern, during operation of the transistor.
While reox layer
14
provides certain benefits to a transistor, some of which have been described above, the reox layer also introduces some disadvantages. For example, the oxidation enhanced diffusion of tip region
11
caused by the growth of reox layer
14
results in the significant deepening of tip region
11
into silicon substrate
10
. Deepening of the tip region has been known to degrade the punch-through characteristics of the transistor, resulting in functionality and reliability problems, and reduces the usable drive current.
Another disadvantage of reox layer
14
is that the growth of this layer can create crystal defects
16
and
17
in the underlying silicon substrate. Defects
16
and
17
are oxide-induced stacking faults which significantly degrade the performance of the transistor. For example, crystal defects are known to increase leakage currents, degrade gate oxide quality, and reduce the breakdown voltage of the transistor. These problems result in poor yield, reliability, and performance of the overall integrated circuit.
SUMMARY OF THE INVENTION
A transistor comprising a deposited dual-layer spacer structure is described along with its method of fabrication. A polysilicon layer is deposited over a gate dielectric, and is subsequently etched to form the polysilicon gate electrode of the transistor. Next, oxide is deposited over the surface of the gate electrode, followed by deposition of a second dielectric layer. Spacers are then formed adjacent to the gate electrode by etching back the second dielectric layer using a substantially anisotropic etch which etches the second dielectric layer faster than it etches the oxide.
Other features and advantages of the present invention will be apparent from the accompanying drawings and the detailed description that follows.


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