Transistor gate electrode having conductor material layer

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation

Reexamination Certificate

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C438S285000, C257SE21182

Reexamination Certificate

active

10745978

ABSTRACT:
Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.

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patent: 6911384 (2005-06-01), Dokumaci et al.
patent: 2002/0105015 (2002-08-01), Minoru et al.
patent: 2003/0227013 (2003-12-01), Currie et al.
patent: 2004/0023478 (2004-02-01), Samavedam et al.
patent: 2005/0087870 (2005-04-01), Adetutu et al.
Wu D et al: “A Novel Strained SIO. 7GEO.3 Surface-Channel PMOSFET With an ALD TIN/AL203/HFALOX/AL203 Gate Stack” IEEE Electron Device Letters, IEEE Inc., New York, US, vol. 24 No. 3, Mar. 2003, pp. 171-173, XP001169959 ISSN: 0741-3106.
Ritenour A. et al: “Epitaxial Strained Germanium p-MOSFETs with Hf02 Gate Dielectric and TaN Gate Electrode,” International Electgronic Devices Meeting 2003. IEDM. Technical Digest. Washington, D.C., Dec. 8-10, 2003, New York, NY: IEEE, USS, Dec. 8, 2003, pgs.

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