Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2007-05-29
2007-05-29
Booth, Richard A. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S285000, C257SE21182
Reexamination Certificate
active
10745978
ABSTRACT:
Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.
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Ritenour A. et al: “Epitaxial Strained Germanium p-MOSFETs with Hf02 Gate Dielectric and TaN Gate Electrode,” International Electgronic Devices Meeting 2003. IEDM. Technical Digest. Washington, D.C., Dec. 8-10, 2003, New York, NY: IEEE, USS, Dec. 8, 2003, pgs.
Boyanov Boyan
Chau Robert
Datta Suman
Doyle Brian S.
Jin Been-Yih
Blakely , Sokoloff, Taylor & Zafman LLP
Booth Richard A.
Intel Corporation
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