Transistor fabrication process in which a contact metallization

Details Transistor fabrication process in which a contact metallization Transistor fabrication process in which a contact metallization

1995-11-20

2000-05-09

Nelms, David

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438626, 438631, 438648, 438649, 438651, 438655, 438664, 438682, 438685, 438691, 438721, H01L 214763

Patent

active

060603879

ABSTRACT:
A new process for creating a transistor in an integrated circuit provides for two suicide formations, each independent of the other, from two metal depositions and formations steps. The process produces a sufficiently low resistance silicide layer over the source/drain region surfaces of the transistor while also creating a lower resistance silicide over the gate interconnects. In an example embodiment of the invention a near-planar isolation process is used applied such that the gate interconnect surfaces are co-planar. A first silicide layer is formed over the source/drain regions. A dielectric gap-fill material is applied. A planarization method such as chemical mechanical polishing is used to remove the gap fill material down to the top surface of the gate interconnect. A relatively thick suicide is then formed over the top surface of the gate interconnect.

REFERENCES:
patent: 4851257 (1989-07-01), Young et al.
patent: 4908332 (1990-03-01), Wu
patent: 5219784 (1993-06-01), Solheim
patent: 5714394 (1998-02-01), Kadosh et al.
patent: 5851916 (1998-12-01), Howard
"Silicon Contact Formation and Photoresist Planarization Using Chemical Mechanical Polishing," Craig L. Keast, et al., VMIC Conference, Jun. 7-8, 1994.

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