Transistor fabrication method

Details Transistor fabrication method Transistor fabrication method

1996-01-16

2002-12-24

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S305000, C438S592000

Reexamination Certificate

active

06498080

ABSTRACT:

TECHNICAL FIELD
This invention relates to semiconductor integrated circuits and to methods for their fabrication.
BACKGROUND OF THE INVENTION
Semiconductor integrated circuits are often fabricated by creating raised topographic features upon a substrate. Then a dopant species is introduced into the substrate with the raised topographic features serving to mask a portion of the substrate. For example, in the fabrication of semiconductor integrated circuits using field effect transistors (FETS), a gate stack (typically including a gate oxide with an overlying body of polysilicon) is formed upon a silicon substrate. Then a dopant species is introduced into a silicon substrate by diffusion or ion implantation to create the source and drain regions on both sides of the gate stack. As the dopant species is introduced, the gate stack serves as a self-aligned mask shielding the channel under the gate from the dopant species.
Of course, during the above-described dopant introduction, the gate stack is subjected to the same environment as the to-be-formed source and drain regions are subjected. For example, if ion implantation techniques are employed to create the source and drain, the gate stack is exposed to ion implantation of the same dopant species as the to-be-formed source and drain regions.
In the past, exposure of the gate stack to ion implantation species has not generally created a problem because the implanted species have been completely absorbed by the gate polysilicon. However, as integrated circuit geometries have continued to shrink, the thickness of gate stacks has also shrunk. If the thickness of the gate is too low relative to the implant dose energy, the implanted species may penetrate through the gate.
Penetration of the implanted species through the gate is often termed “channeling.” If the energy of the implanted species is great enough and the polysilicon grains are oriented with the direction of the implant species, then the range of implanted species becomes greater than the thickness of the gate stack, and the implanted species may arrive at the gate oxide-silicon interface with enough energy to penetrate into or perhaps through the gate oxide. Thus, channeling depends upon the size and orientation of the polysilicon, as well as the energy of the implant species. A single large grain, if oriented parallel to the implant direction, can permit channeling.
When channeling occurs, the silicon surface beneath the gate may be inverted, leading to transistor leakage and/or shifts in the threshold voltage. Another adverse affect of channeling is gate oxide degradation. In addition, channeling may cause flat band voltage shifts in polysilicon capacitors in the same integrated circuit. Heretofore, the channeling problem has not posed a serious obstacle to integrated circuit designers because gate stacks in previous generation integrated circuits have been thick enough to prevent channeling.
SUMMARY OF THE INVENTION
These problems are alleviated by the present invention which illustratively includes:
forming a dielectric layer upon a substrate;
forming a conductive layer upon the dielectric layer;
forming a material layer overlying the conductive layer;
forming a patterned resist upon the material layer;
at least partially etching the material layer to form a raised feature;
removing the resist;
using the raised feature as a mask, anisotropically etching the conductive layer and the dielectric layer, thereby forming a gate;
forming a source and drain region; and
removing the mask.


REFERENCES:
patent: 4697333 (1987-10-01), Nakahara
patent: 4950618 (1990-08-01), Sundaresan et al.
patent: 5084417 (1992-01-01), Joshi et al.
patent: 5185279 (1993-02-01), Ushiku
patent: 5217923 (1993-06-01), Sugaro
patent: 5268317 (1993-12-01), Schwalke et al.
patent: 5395780 (1995-03-01), Hwang
Wolf, “Silicon Processing for the VLSI Era, vol. II”, p. 273-275, 1990.

Affiliated with

Also associated with

Rating

Transistor fabrication method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Transistor fabrication method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Transistor fabrication method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2978648